Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • Method for detecting thinning of the substrate of an integrated circuit from its back side, and associated integrated circuit
    Patent number: 10770409
    Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Christian Rivero, Quentin Hubert
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 10770547
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Protection of an NFC router against overvoltage
    Patent number: 10770891
    Abstract: The invention relates to a device for protecting a near field communication router against possible over-voltages picked up by an antenna. The device includes two voltage-limiter elements between terminals of the antenna and a ground. A circuit detects the presence of an electromagnetic field in the vicinity of an operating frequency of the router, and controls the limiter elements, the limiter elements being active by default.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Integrated circuit with improved resistive region
    Patent number: 10770357
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • Device comprising a stack of electronic chips
    Patent number: 10770411
    Abstract: A method of protecting a first chip in a multi-chip stack includes determining an electrical characteristic of a conductive loop. The conductive loop extends over a top portion of the first chip. The conductive loop also extends through the first chip and within a top portion of a second chip. The top portion of the second chip is adjacent to a bottom portion of the first chip. The method further includes determining whether the electrical characteristic indicates that an attack is being made to determine contents or operation of the first chip.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Clement Champeix, Nicolas Borrel
  • Device and method for managing the current consumption of an integrated module
    Patent number: 10769513
    Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas, Yanis Linge, Jimmy Fort
  • Glitch detection of a DC voltage
    Patent number: 10768229
    Abstract: A circuit for detecting a glitch in power supply includes a detection circuit to detect the glitch in a DC supply voltage of the power supply when a magnitude in the glitch in a DC supply voltage of the power supply exceeds a detection threshold, wherein the detection threshold is a function of the DC supply voltage, and wherein the detection circuit comprises a low pass filter, a control circuit coupled to the low pass filter, and a current mirror circuit coupled to the control circuit having an output for providing a logic signal indicative of a detected glitch.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Nicolas Borrel, Jimmy Fort
  • Integrated circuit having a hidden shared contact
    Patent number: 10763213
    Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 1, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • DEVICE OF PHYSICALLY UNCLONABLE FUNCTION WITH FLOATING GATE TRANSISTORS, AND MANUFACTURING METHOD
    Publication number: 20200274723
    Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of floating gate transistor pairs, floating gate transistors of the set of floating gate transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of floating gate transistor pairs of the set of floating gate transistor pairs, and to identify a floating gate transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable floating gate transistor pair; and a write circuit configured to shift the effective threshold voltage of a floating gate transistor of the unreliable floating gate transistor pair to be inside the common random distribution.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 27, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • METHOD AND DEVICE FOR ON-BOARD DETECTION OF POTENTIAL FAULTS IN A SYSTEM FIXED ONTO THE BOARD
    Publication number: 20200271716
    Abstract: An electronic assembly includes a board and a system mounted to the board. The system includes an impedance matching circuit coupled to a contactless component. A detection circuit operates to carrying out a process for detecting on the board of potential faults in the system mounted to the board. The detection circuit includes a circuit incorporated into the contactless component itself and configured to carrying out a first part of the process for detecting. A processing circuit of the detection circuit performs a second part of the process for detecting based on results of the first part.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 27, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Nicolas CORDIER
  • Random number generator
    Patent number: 10754618
    Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit Froment, Sebastien Petitdidier, Mathieu Lisart, Jean-Marc Voisin
  • Switched mode power supply circuit
    Patent number: 10756628
    Abstract: An electronic circuit includes a switched-mode power supply powering a first load via a first linear voltage regulator. The first regulator includes a transistor. The substrate and the gate of the transistor are capable of being coupled to a node of application of a power supply voltage. A method of operating the circuit is also disclosed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: August 25, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Michel Cuenca, Cedric Thomas
  • NON-VOLATILE MEMORY WITH DOUBLE CAPA IMPLANT
    Publication number: 20200265894
    Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francois TAILLIET, Roberto SIMOLA
  • Evaluation of an average power consumption of an electronic circuit
    Patent number: 10749576
    Abstract: A device includes an electronic circuit and a voltage-controlled oscillator configured to receive information representative of a power supply voltage of the device. The voltage-controlled oscillator is coupled to the electronic circuit. A first counter is configured to count pulses supplied by the voltage-controlled oscillator and a second counter is configured to count pulses of a clock signal. The device is configured to estimate an average power of the electronic circuit based on the pulses counted by the first counter.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: August 18, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Near-field communication circuit, interface, and system
    Patent number: 10749572
    Abstract: A circuit includes a near-field communication circuit configured to receive a radio frequency control signal transmitted in a near-field regime, a pulse width modulation signal generation circuit coupled to the near-field communication circuit circuit and configured to generate a pulse width modulation signal according to the radio frequency control signal, and a non-volatile memory coupled to both the near-field communication circuit circuit and the pulse width modulation signal generation circuit, the non-volatile memory comprising digital words for configuring the pulse width modulation signal.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 18, 2020
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GRENOBLE2) SAS
    Inventors: Gwenael Maillet, Jean-Louis Labyre, Gilles Bas
  • Integrated mechanical device with vertical movement
    Patent number: 10748726
    Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 18, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio Di-Giacomo, Brice Arrazat
  • Motor control system
    Patent number: 10742145
    Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 11, 2020
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Gwenael Maillet, Jean-Louis Labyre, Gilles Bas
  • Method for managing transactions routing between source equipment and target equipment
    Patent number: 10740141
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Electronic chip architecture
    Patent number: 10734329
    Abstract: In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Thomas Ordas
  • Method of writing in a non-volatile memory device and corresponding non-volatile memory device
    Patent number: 10732894
    Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista