Patents Assigned to STMICROELECTRONICS (ROUSSET)
  • METHOD FOR DETECTING A DIFFERENTIAL FAULT ANALYSIS ATTACK AND A THINNING OF THE SUBSTRATE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT
    Publication number: 20210057358
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed to detect a DFA attack by fault injection into the integrated circuit.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Abderrezak MARZAKI
  • Method and apparatus for monitoring scene detection
    Patent number: 10929724
    Abstract: A method is provided for monitoring scene detection by an apparatus detecting scenes from among a set of possible reference scenes. It includes an assignment of an identifier to each reference scene, detection of scenes from among the set of possible reference scenes at successive instants of detection with the aid of at least one classification algorithm, and a sliding time filtering processing of these detected current scenes over a filtering window of size M, based on the identifier of each new detected current scene taken into account in the window and a confidence probability associated with this new detected current scene, the output of the filtering processing successively delivering filtered detected scenes.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pierre Demaj, Laurent Folliot
  • Compact non-volatile memory device
    Patent number: 10930351
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • Protection against rerouting a communication channel of a telecommunication device having an NFC circuit and a secure data circuit
    Patent number: 10931712
    Abstract: A method and associated circuits protect data stored in a secure data circuit of a telecommunication device equipped with a near-field communication (NFC) router, a microcontroller, and the secure data circuit. In the method, each message received with the NFC router is parsed to retrieve a communication pipe identifier and an instruction code. The communication pipe identifier and the instruction code are compared to corresponding information in a filter table. Instruction codes of particular messages that attempt to modify a communication pipe by reassigning one end of the communication pipe from the port of the NFC router to a different circuit are acted upon. These messages are blocked from reaching the secure data circuit when the instruction code is not authorized in the filter table, and these messages are permitted when the instruction code is authorized in the filter table.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: February 23, 2021
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Thierry Huque, Olivier Van Nieuwenhuyze, Alexandre Charles
  • Method of manufacturing MOS transistor spacers
    Patent number: 10930757
    Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 23, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Arnaud Regnier, Dann Morillon, Franck Julien, Marjorie Hesse
  • Configuration of NFC routers for P2P communication
    Patent number: 10931519
    Abstract: A method for configuring a first device for a near-field communication with a second device, wherein a peer-to-peer mode is selected if the second device draws the power supply of its circuits from a battery.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 23, 2021
    Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Olivier Van Nieuwenhuyze, Alexandre Charles
  • SWITCHED-MODE POWER SUPPLY
    Publication number: 20210050785
    Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien ORTET, Didier DAVINO, Cedric THOMAS
  • Integrated circuit including at least one memory cell with an antifuse device
    Patent number: 10923484
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: February 16, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • PROCESS FOR FABRICATING MEDIUM-VOLTAGE TRANSISTORS AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20210035996
    Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Franck JULIEN, Abderrezak MARZAKI
  • FABRICATION PROCESS COMPRISING AN OPERATION OF DEFINING AN EFFECTIVE CHANNEL LENGTH FOR MOSFET TRANSISTORS
    Publication number: 20210036126
    Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Franck JULIEN
  • Monitoring of a DC voltage value with respect to several voltage levels
    Patent number: 10908192
    Abstract: A method includes selecting at least one first voltage that defines subsets of DC voltages from among an ordered set of DC voltages, comparing the first voltage with a DC reference voltage, selecting one of the subsets based on a result of the comparing, and comparing each voltage of the selected subset with the reference voltage.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Bruno Gailhard
  • SWITCHED-MODE POWER SUPPLY
    Publication number: 20210028700
    Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.
    Type: Application
    Filed: July 20, 2020
    Publication date: January 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Michel CUENCA, Sebastien ORTET
  • METHOD FOR PROTECTING DATA STORED IN A MEMORY, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20210028128
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • STARTING OF A SWITCHED-MODE POWER SUPPLY
    Publication number: 20210028687
    Abstract: The process for starting a power supply circuit which includes a switched-mode power supply is performed using: a first phase during which, if an output voltage of the switched-mode power supply is lower than a first voltage, the switched-mode power supply operates in pulse width modulation mode to increase its output voltage up to said first voltage; and when the output voltage has reached the first voltage, a second phase during which the switched-mode power supply operates in a bypass mode.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien ORTET, Cedric THOMAS
  • MOS transistors in parallel
    Patent number: 10903209
    Abstract: An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: January 26, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • METHOD FOR DETECTING MOISTURE IN AN INTEGRATED CIRCUIT, AND ASSOCIATED INTEGRATED CIRCUIT
    Publication number: 20210018458
    Abstract: Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 21, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Matthias VIDAL-DHO, Quentin HUBERT, Pascal FORNARA
  • Device and method for switching an electrical system into standby mode
    Patent number: 10895856
    Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: January 19, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • METHOD FOR MANAGING THE STARTUP OF A PHASE-LOCKED LOOP AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20210013893
    Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 14, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Bruno GAILHARD, Laurent TRUPHEMUS, Christophe EVA
  • Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit
    Patent number: 10892234
    Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre Sarafianos, Abderrezak Marzaki
  • MOS transistors in parallel
    Patent number: 10892321
    Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: François Tailliet