Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.

Abstract: Circuits and methods of operating multiple antennas using a shared controller are provided. In one embodiment, a method includes coupling, in a first configuration, a first antenna to the shared controller and decoupling a second antenna from the shared controller. The first antenna is coupled to the shared controller using a first matching circuit and a first filter. The method further includes operating a controllable activation component to define a second configuration state formed by decoupling the first antenna from the shared controller and coupling the second antenna to the shared controller. In this embodiment, the second antenna is coupled to the shared controller using a second matching circuit and a second filter. At least one capacitor of the first matching circuit is used in the second filter and at least one capacitor of the second matching circuit is used in the first filter.

Abstract: A cover for an electronic circuit package, including an element having peripheral portions housed in an inner groove of a through opening.

Abstract: A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.

Abstract: A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.

Abstract: An electronic converter includes first and second inputs, first and second outputs, and a switching cell configured to supply current. The switching cell includes a half-bridge including first and second switches connected in series between the two inputs. The half-bridge includes a intermediate point between the first and second switch, a first inductor directly connected to the first output, a second inductor connected to the intermediate point, a first capacitor connected in series with the first and second inductors, a second capacitor connected between the intermediate point and the second input, and a circuit connected between a terminal of the first inductor and the second output. A circuit path of the converter is configured to couple the second inductor with the first output through the first capacitor and the first inductor, and another circuit path is configured to couple the second capacitor with the first output through the first inductor.

Abstract: A Pseudo-Random Noise code generator module is configured to generate PRN codes operating with different navigation standards for use with a GNSS receiver. The generator includes a number of linear shift registers including a respective number of feedback taps and a channel selection network including an output multiplexer. A first register includes a first number of taps and a second register includes a second number of taps. The first register and second register are associated with a respective feedback network to combine signals at the feedback taps to obtain a feedback signal that is selectably fed back through a selection circuit at an input of the respective register. A network can selectably concatenate the first register with the second register.

Abstract: A time-of-flight (TOF) imaging system includes illumination circuitry, such as a laser, one or more sensors, such as SPAD arrays, and image processing circuitry. The illumination circuitry illuminates one or more objects in an environment around the TOF imaging system. The sensors generate an image data stream based on reflections from the one or more illuminated objects, and possibly based on reflections from one or more reflectors. The image processing circuitry generates counts associated with distances based on the image data stream and possibly a reflection data stream and stores the generated counts in a histogram using a plurality of bins. Each of the plurality of bins stores counts associated with a respective distance range. A size of a bin in the plurality of bins is a function of the respective distance range, and may be based on a logarithmic function of the distance associated with the bin.

Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

Abstract: A microneedle array device includes a substrate and an array of microneedles on the substrate. Each microneedle includes a redox enzyme and redox mediator and an electrically conductive layer on the substrate. The electrically conductive layer may extend partway up each microneedle exposing the tip thereof.

Abstract: A method of processing a visible light communication (VLC) signal using a single-photon avalanche diode (SPAD) includes detecting photons of a VLC signal at a SPAD detector, counting the photons detected by the SPAD detector to generate a combined VLC signal comprising a data signal and an ambient signal, extracting the ambient signal from the combined VLC signal, subtracting the ambient signal from the combined VLC signal to generate the data signal, and outputting the data signal as a bitstream.

Abstract: Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

Abstract: An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.

Abstract: A method for transmitting power includes providing power using a contactless power transfer from a transmitter to a receiver that is mutually coupled with the transmitter. The method also includes managing and regulating the contactless power transfer being provided, where the managing and regulating are integrally and autonomously performed by the transmitter.

Abstract: A MEMS device includes a semiconductor support body having a first cavity, a membrane including a peripheral portion, fixed to the support body, and a suspended portion. A first deformable structure is at a distance from a central part of the suspended portion of the membrane and a second deformable structure is laterally offset relative to the first deformable structure towards the peripheral portion of the membrane. A projecting region is fixed under the membrane. The second deformable structure is deformable so as to translate the central part of the suspended portion of the membrane along a first direction, and the first deformable structure is deformable so as to translate the central part of the suspended portion of the membrane along a second direction.

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

Abstract: An integrated circuit, includes: an input configured to receive an induced signal that is modulated according to a protocol belonging to the group including protocols using ASK modulation and protocols using OOK modulation; a detection circuit configured to detect the modulation of the induced signal; a decoding circuit configured to detect the protocol; a configurable limiter configured to limit a level of the induced signal and having a first configuration adapted to protocols using ASK modulation and a second configuration adapted to protocols using OOK modulation; and a control circuit configured to set the limiter in the first configuration until a protocol is detected, and to switch the limiter from the first configuration to the second configuration in response to a protocol using OOK modulation being detected.

Abstract: A microelectronic device includes a chip housing a functional part and carrying first electrical contact regions in electrical connection with the functional part through first protected connections extending over or in the chip. A substrate has a first contact area and a second contact area, which is remote from the first contact area. The first contact area carries second electrical contact regions, and the second contact area carries external connection regions. The second contact regions and the external connection regions are in mutual electrical connection through second protected connections extending over or in the substrate. A protection-ring structure surrounds the first and second electrical contact regions and delimits a first chamber closed with respect to the outside. The first electrical contact regions and the second electrical contact regions are in mutual electrical contact.

Abstract: A device to read a variable resistor has an analog to digital converter (ADC), a first switch and a second switch. The ADC has a first ADC input, a second ADC input and an ADC output. The first switch selectively couples a first voltage indicative of a voltage across a first resistance to the first ADC input. The second switch selectively couples a second voltage indicative of a voltage across a second resistance to the second ADC input. The ADC outputs a signal indicative of a value of the second resistance.

Abstract: A fluid ejection device, comprising: a chamber; a membrane, with a first side and a second side opposite to one another, where the first side faces the chamber; an actuator, of a piezoelectric type, which extends on the second side of the membrane and is operatively coupled to the membrane for causing, in use, a vibration of the membrane; a passivation layer, which extends only alongside, or partially on, the actuator; and a protection layer, which extends on the actuator at least in surface portions of the latter that are free from the passivation layer, and has a Young's modulus lower than the Young's modulus of the passivation layer.