Abstract: A method is provided for controlling an electronic apparatus on the basis of a value of a lid angle between a first hardware element accommodating a first magnetometer and a second hardware element accommodating a second magnetometer. The method includes acquiring, through the magnetometers, first signals representing an orientation of the hardware elements. A calibration parameter indicative of a condition of calibration of the magnetometers is generated on the basis of the first signals. A reliability value indicative of a condition of reliability of the first signals is generated on the basis of the first signals. A first intermediate value of the lid angle is calculated on the basis of the first signals. A current value of the lid angle is calculated on the basis of the calibration parameter, of the reliability value, and of the first intermediate value, and the electronic apparatus is controlled on the basis of the current value.

Abstract: A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Abstract: A sensor device includes a passive infrared sensor, a control circuit, and a lens that directs infrared radiation onto the passive infrared sensor. The lens includes an obstruction that asymmetrically blocks transmission of infrared radiation through the lens. The control circuit is configured to determine the direction of crossing of individuals passing in front of the sensor device based on sensor signals from the passive infrared sensor.

Abstract: The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.

Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pattern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.

Abstract: A switching regulator circuit has a high side (HS) transistor actuated during on time (TON) of a duty cycle. The output current of the switching regulator circuit is determined from sensing a transistor current flowing through the HS transistor during HS transistor on time (TON) and dividing the sensed transistor current by the duty cycle to generate an output signal indicative of the output current of the switching regulator circuit. The duty cycle is determined from a ratio of the on time (TON) and off time (TOFF) of the switching regulator circuit.

Abstract: Disclosed herein is a microelectromechanical (MEMS) device, including a rotor and a first piezoelectric actuator mechanically coupled to the rotor. The first piezoelectric actuator is electrically coupled between a first signal node and a common voltage node. A second piezoelectric actuator is mechanically coupled to the rotor, and is electrically coupled between a second signal node and the common voltage node. Control circuitry includes a drive circuit configured to drive the first and second piezoelectric actuators, a sense circuit configured to process sense signals generated by the first and second pizeoelectric actuators, and a multiplexing circuit. The multiplexing circuit is configured to alternate between connecting the drive circuit to the first piezoelectric actuator while connecting the sense circuit to the second piezoelectric actuator, and connecting the drive circuit to the second piezoelectric actuator while connecting the sense circuit to the first piezoelectric actuator.

Abstract: A microelectromechanical device includes: a support body; at least one movable mass of semiconductor material, elastically constrained to the support body so as to be able to oscillate; fixed detection electrodes rigidly connected to the support body and capacitively coupled to the at least one movable mass; and at least one test structure of semiconductor material, rigidly connected to the support body and distinct from the fixed detection electrodes. The test structure is capacitively coupled to the at least one movable mass and is configured to apply electrostatic forces to the at least one movable mass in response to a voltage between the test structure and the at least one movable mass.

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

Abstract: A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.

Abstract: The present disclosure is directed to a method of forming a conductive trace in a substrate. A pattern of the trace is formed in the substrate by a laser machining technique. The pattern of the trace is covered by palladium colloid. The palladium colloid is transferred to the patterned substrate by a laser-induced forward transfer (LIFT) technique. The palladium colloid is converted to a palladium plating catalyst layer by a palladium acceleration process. The palladium plating catalyst layer provides a sufficient catalyst to grow a metal seeding layer by an electroless copper deposition technique. In addition, the palladium plating catalyst layer includes portions of tin material which increases adhesion of the metal seeding layer into the substrate. After growing the metal seeding layer, the pattern of the trace is filled by a copper layer through an electrochemical deposition technique.

Abstract: In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.

Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.

Abstract: One or more semiconductor dice are arranged on a die pad of a leadframe having an array of electrically conductive leads around the die pad. A pattern of electrically conductive wires is provided to couple the semiconductor die or dice with electrically conductive leads in the array around the die pad. An encapsulation of insulating material is provided to encapsulate the semiconductor die or dice arranged on the die pad and the pattern of electrically conductive wires.

Abstract: A body of semiconductor material has a surface and accommodates an active area, conductive regions, a first deep insulation structure extending in the active area from the surface of the body in a first trench, and a second deep insulation structure extending in the active area from the surface of the body in a second trench and surrounding the conductive regions. The first deep insulation structure has insulation walls surrounding a conductive filling portion. The second deep insulation structure has a solid insulating region filling the second trench. The first deep insulation region has a first width and a first depth and the second deep insulation structure has a second width and a second depth. The second width is smaller than the first width and the second depth is smaller than the first depth.

Abstract: Electrically insulating material such as an epoxy resin is molded onto a sculptured, electrically conductive leadframe structure comprising a pattern of electrically conductive formations. The electrically insulating material penetrates into spaces between electrically conductive formations in the pattern of electrically conductive formations to provide a pre-molded leadframe structure configured to have at least one semiconductor die arranged thereon. The pre-molded leadframe structure has opposed first and second surfaces and a pre-molded leadframe thickness between the first surface and the second surface. The sculptured, electrically conductive leadframe structure comprises one or more connection formations connected with electrically conductive formations in the pattern of electrically conductive formations. The connection formation or formations have a first thickness equal to the thickness between the first surface and the second surface.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: MEMS device comprising: a signal processing assembly; a transduction module comprising a plurality of transducer devices; a stiffening structure at least partially surrounding each transducer device; one or more coupling pillars for each transducer device, extending on the stiffening structure and configured to physically and electrically couple the transduction module to the signal processing assembly, to carry control signals of the transducer devices. Each conductive coupling element has a section having a shape such as to maximize the overlapping surface with the stiffening structure around the respective transducer device. This shape includes hypocycloid with a number of cusps equal to or greater than three; triangular; quadrangular.

Abstract: A sensor device includes an infrared sensor configured to generate sensor data. The sensor device also includes a configurable digital analysis block. The configurable digital analysis block is configured to generate classification data based on the sensor data. The configurable digital analysis block includes a plurality of selectable analysis blocks that can be selectively included in generating the classification data.

Abstract: A method of managing an integrated circuit memory includes identifying a set of allocated regions and a set of empty regions spanning a memory space of an integrated circuit card, selecting the biggest empty region of the set of empty regions, determining that an allocated memory block of an allocated region immediately adjacent to the biggest empty region is larger than the biggest remaining empty region of the memory space, storing the allocated memory block in a temporary list of skipped memory blocks, removing the allocated memory block from the set of allocated memory regions, and swapping the allocated memory block with a remaining empty region to widen the biggest empty region.