Patents Assigned to STMicroelectronics S.A.
  • Publication number: 20240045030
    Abstract: A LIDAR optical unit includes a photonic-integrated-circuit (PIC) affixed to a carrier. The PIC includes an input coupler and an array of output couplers, with a switchable optical network connecting the input coupler to different selected ones of the array of output couplers. A laser source is mounted to the PIC adjacent the input coupler such that laser light generated by the laser source is injected into the input coupler. An optical stack is mounted to the PIC adjacent the array of output couplers to receive laser light extracted from the switchable optical network by the array of output couplers. The optical stack includes an array of microlenses positioned so that a bottom surface thereof is mounted to the PIC, and an array of microprisms is stacked on the array of microlenses so that a bottom surface thereof is mounted to a top surface of the array of microlenses.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Antonio FINCATO
  • Publication number: 20240044647
    Abstract: The present disclosure is directed to a device configured to detect whether the device is in a bag or outside of the bag. The device determines whether the device is in or outside of the bag based on distance measurements generated by at least one proximity sensor and motion measurements generated by at least one motion sensor. By using both distance measurements and motion measurements, the device is able to detect whether the device is in the bag or outside of the bag with high accuracy and robustness.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Stefano Paolo RIVOLTA, Federico RIZZARDINI, Lorenzo BRACCO, Roberto MURA
  • Patent number: 11894432
    Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Crocifisso Marco Antonio Renna, Antonio Landi, Brunella Cafra
  • Patent number: 11891298
    Abstract: A process for manufacturing MEMS devices, includes forming a first assembly, which comprises: a dielectric region; a redistribution region; and a plurality of unit portions. Each unit portion of the first assembly includes: a die arranged in the dielectric region; and a plurality of first and second connection elements, which extend to opposite faces of the redistribution region and are connected together by paths that extend in the redistribution region, the first connection elements being coupled to the die. The process further includes: forming a second assembly which comprises a plurality of respective unit portions, each of which includes a semiconductor portion and third connection elements; mechanically coupling the first and second assemblies so as to connect the third connection elements to corresponding second connection elements; and then removing at least part of the semiconductor portion of each unit portion of the second assembly, thus forming corresponding membranes.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Fabio Quaglia, Marco Ferrera, Marco Del Sarto
  • Patent number: 11894810
    Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mattia Fausto Moretti, Paolo Pulici, Alessio Facen
  • Patent number: 11894052
    Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 6, 2024
    Assignees: STMicroelectronics S.r.l., Alma Mater Studiorum—Universita' Di Bologna
    Inventors: Marco Pasotti, Marcella Carissimi, Alessio Antolini, Eleonora Franchi Scarselli, Antonio Gnudi, Andrea Lico, Paolo Romele
  • Patent number: 11894290
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Patent number: 11894657
    Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 6, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Romeo Letor, Vanni Poletto, Antoine Pavlin, Nadia Lecci, Alfio Russo
  • Patent number: 11892518
    Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first current and the second current activated, respectively, a first voltage drop and a second voltage drop between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first voltage drop and the second voltage drop sensed with the first current and the second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Orazio Pennisi, Valerio Bendotti, Vanni Poletto, Vittorio D'Angelo
  • Publication number: 20240038604
    Abstract: A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Luca CECCHETTO, Alessandra Piera MERLINI, Gabriella ADDESA
  • Publication number: 20240039391
    Abstract: A control circuit for a switching stage of an electronic converter is described. The control circuit includes a driver circuit configured to generate one or more drive signals as a function of a Pulse-Width Modulation, PWM, signal and a PWM signal generator circuit configured to generate the PWM signal. A first comparator asserts a comparison signal when a feedback signal having a voltage being indicative of a current flowing through an inductance of the switching stage is greater than a reference signal. In response to a clock signal, a storage element asserts the PWM signal, whereby the clock signal indicates the duration of the switching period of the PWM signal. Conversely, in response to determining that the comparison signal is asserted, the storage element de-asserts the PWM signal. Specifically, the reference signal is generated as a function of the voltage at a capacitance.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Fabio CACCIOTTO
  • Publication number: 20240038636
    Abstract: A semiconductor die mounting substrate, such as a pre-molded leadframe, is provided with die pads, wherein each die pad has opposed first and second surfaces as well as tie bars projecting therefrom. Semiconductor dice are mounted at the first surface of the die pads. A molding encapsulation material surrounds the semiconductor dice mounted at the first surface of the die pads to produce semiconductor devices, with the semiconductor devices being mutually coupled via the tie bars. The tie bars are then cut transverse to their longitudinal direction at an intermediate singulation location to singulate the semiconductor devices into individual semiconductor devices. The tie bars have a hollowed-out portion with a channel-shaped cross-sectional profile at the intermediate singulation location. Easier-to-cut tie bars can be provided without impairing their stiffness in comparison with tie bars having full rectangular/square cross-sectional shapes.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Dario VITELLO
  • Publication number: 20240036019
    Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS PTE LTD
    Inventors: Malek BRAHEM, Hatem MAJERI, Olivier LE NEEL, Ravi SHANKAR, Enrico Rosario ALESSI, Pasquale BIANCOLILLO
  • Publication number: 20240034618
    Abstract: A microelectromechanical membrane transducer includes: a supporting structure; a cavity formed in the supporting structure; a membrane coupled to the supporting structure so as to cover the cavity on one side; a cantilever damper, which is fixed to the supporting structure around the perimeter of the membrane and extends towards the inside of the membrane at a distance from the membrane; and a damper piezoelectric actuator set on the cantilever damper and configured so as to bend the cantilever damper towards the membrane in response to an electrical actuation signal.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Domenico GIUSTI, Fabio QUAGLIA
  • Publication number: 20240036595
    Abstract: A low-drop out voltage regulator includes a pass element arranged between an input terminal and an output terminal, a feedback network configured to produce a feedback voltage derived from an output voltage, and an error amplifier configured to drive the pass element as a function of a difference between the feedback voltage and a reference voltage. An output transistor coupled in series with the pass element is controlled by a mode selection circuit. In response to assertion of a mode selection signal, the mode selection circuit turns on the output transistor to sink a current with a controlled magnitude from the output node. In response to de-assertion of the mode selection signal, the mode selection circuit sinks a current with a controlled magnitude from a control terminal of the output transistor to turn off the output transistor at a controlled rate.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Umberto FERLITO, Michele VAIANA, Giuseppe BRUNO, Alfio Dario GRASSO
  • Publication number: 20240038650
    Abstract: Semiconductor devices of the type currently referred to as a System in a Package (SiP) and having embedded therein a transformer are produced by embedding at least one semiconductor chip in an insulating encapsulation at a first portion thereof. Over a second portion thereof at least partly non-overlapping with the first portion, a stacked structure is formed including multiple layers of electrically insulating material as well as respective patterns of electrically conductive material. The respective patterns of electrically conductive material have: a planar coil geometry for providing electrically conductive coils such as the windings of a transformer and a geometrical distribution providing electrically conductive connections to one or more semiconductor chips.
    Type: Application
    Filed: July 19, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Damian HALICKI, Michele DERAI
  • Patent number: 11887584
    Abstract: A method to detect a vocal command, the method including: analyzing audio data received from a transducer configured to convert audio into an electric signal and analyzing the data using a first neural network. The method also includes detecting a keyword from the audio data using the first neural network on the edge device, the first neural network being trained to recognize the keyword. The method further includes activating a second neural network after the keyword is identified by the first neural network and analyzing the audio data using the second neural network, the second neural network being trained to recognize a set of vocal commands. The method to detect a vocal command may also include detecting the vocal command word using the second neural network.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nunziata Ivana Guarneri, Viviana D'Alto
  • Patent number: 11888400
    Abstract: In an embodiment, an USB interface includes a transformer, a primary winding of the transformer and a first switch connected in series between a first node and a second node, a secondary winding of the transformer and a component connected in series between a third node and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 30, 2024
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Jean Camiolo, Francesco Ferrazza, Nathalie Ballot
  • Patent number: 11888304
    Abstract: An integrated circuit with a hot-plug protection circuit includes input pins and an output pin. The input pins are electrically coupled to a common node in the hot-plug protection circuit via respective electrical connections. The integrated circuit includes clamping circuitry coupled between the common node and the output pin, the clamping circuitry activatable as a result of a voltage spike applied across the clamping circuitry. The plurality of electrical connections and the clamping circuitry provide respective current discharge paths between the input pins in the input pins and the output pin, the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of the input pins in the plurality of input pins being transferred to the common node via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Vittorio D'Angelo, Salvatore Cannavacciuolo, Sergio Lecce, Valerio Bendotti, Orazio Pennisi
  • Patent number: 11889765
    Abstract: A MEMS device is provided that includes a semiconductor substrate including a main surface extending perpendicular to a first direction and a side surface extending on a plane parallel to the first direction and to a second direction that is perpendicular to the first direction. At least one cantilevered member protrudes from the side surface of the semiconductor substrate along a third direction that is perpendicular to the first and second directions. The at least one cantilevered member includes a body portion that includes a piezoelectric material. The body portion has a length along the third direction, a height along the first direction and a width along the second direction, and the height is greater than the width. The at least one cantilevered member is configured to vibrate by lateral bending along a direction perpendicular to the first direction.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 30, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Gianluca Longoni, Luca Seghizzi