Abstract: An optical semiconductor package includes a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support has, in the passage, at least one local release recess and the ring is equipped peripherally with a locally projecting, elastically deformable element. The local release recess and the elastically deformable element are such that, when the ring occupies an angular mounting position, the locally projecting elastically deformable element is engaged in the local recess of the support and, when the ring is pivoted from the aforementioned angular mounting position, the locally projecting elastically deformable element is moved out of the recess of the support and is compressed against the wall of the passage in order to secure the ring relative to the support.

Abstract: A frequency shift of a carrier frequency of an input signal is estimated with a frequency estimator in order to obtain an estimate value. Then, the estimate of the frequency shift is refined, and the carrier frequency is corrected in consequence, with a phase-locked loop that is initialized with the estimate value. The phase-locked loop has a locking frequency range that is narrower than a locking frequency range of the frequency estimator.

Abstract: A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.

Abstract: A device for protecting a circuit against a polarity reversal of a connection to a D.C. power supply, comprising a controllable switch interposed on said connection between a first terminal of a first voltage of the D.C. power supply and a first terminal of the circuit, and first means for turning-off with a delay the switch in the presence of a reverse polarity.

Abstract: Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

Abstract: A passive contactless integrated circuit includes an electrically programmable non-volatile data memory (MEM), a charge accumulation booster circuit for supplying a high voltage necessary for writing data in the memory. The integrated circuit includes a volatile memory point for memorizing an indicator flag, and circuitry for modifying the value of the indicator flag when the high voltage reaches a critical threshold for the first time after activating the booster circuit.

Abstract: A circuit for providing an A.C. signal including a number N of nanomagnetic oscillators, N being an integer greater than or equal to 2, each nanomagnetic oscillator providing a periodic signal; a unit for providing a control signal that can take N values, each periodic signal being associated with one of the values of the control signal; and a multiplexer receiving the N periodic signals and the control signal and providing the A.C. signal equal to one of the periodic signals according to the value of the control signal.

Abstract: An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

Abstract: An encapsulated organic electronic device is provided with: a substrate; at least one first elementary component and one second elementary component set above the substrate, each of said first and second elementary components being provided with a respective first electrode set above the substrate, a respective region of organic material set above the first electrode, and a respective second electrode set above the region of organic material at least partially in an area corresponding to the first electrode; and an encapsulation structure, defining an encapsulation space isolated from an external environment and designed to protect the first and second elementary components from the external environment. In particular, the regions of organic material of the first and second elementary components are separated and distinct from one another and are set entirely within the encapsulation space.

Abstract: A driving mass of an integrated microelectromechanical structure is moved with a rotary motion about an axis of rotation, and a sensing mass is connected to the driving mass via elastic supporting elements so as to perform a detection movement in the presence of an external stress. The driving mass is anchored to a first anchorage arranged along the axis of rotation by first elastic anchorage elements. The driving mass is also coupled to a pair of further anchorages positioned externally thereof and coupled to opposite sides with respect to the first anchorage by further elastic anchorage elements; the elastic supporting elements and the first and further elastic anchorage elements render the driving mass fixed to the first sensing mass in the rotary motion, and substantially decoupled from the sensing mass in the detection movement, the detection movement being a rotation about an axis lying in a plane.

Abstract: Measurements are acquired from a magnetic sensor during a non-pre-ordered movement, and a plurality of sets of solutions are determined for respective expected values of intensity of the Earth's magnetic field. The solutions are defined by a plurality of parameters, including at least one gain value for each detection axis of the magnetic sensor. For each solution, a figure of merit is determined, correlated to a calibration error, and a partial solution is selected in each set of solutions, based on the figure of merit. Once a gain confidence interval has been defined, a calibration solution is selected based on the figure of merit, from among the partial solutions having respective gain values all falling within the gain confidence interval.

Abstract: A spiral structure having at least one planar winding in at least one first conductive level to form at least one inductive element, wherein the winding is surrounded with a conductive plane and at least one track is formed in a second conductive level and has two ends connected by conductive vias to the plane of the first level, at diametrically opposite positions with respect to the center of the winding.

Abstract: A method of channel estimation in orthogonal frequency-division multiplexing communication employing three or more subcarriers, wherein frequency correlation exists between the subcarriers. The method includes: calculating a coarse channel estimate for each of the subcarriers, and calculating from the coarse channel estimates refined channel estimates for each of the subcarriers, wherein calculation of the refined channel estimates includes calculating the parameters of a Wiener Filter having a length of 2 L+1, where L is a positive integer, and filtering the coarse channel estimates with the Wiener Filter.

Abstract: An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

Abstract: An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed on the surface layer and connected respectively to the multiplicities of vias.

Abstract: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied to a second circuit portion with transistors. The output of the first circuit portion is coupled to ground by a discharge transistor. A third circuit portion with transistors receives a third voltage transformed, starting from the second voltage for biasing at least one word line connected downstream of the third circuit portion. A circuit portion with a discharge switch incorporates the discharge transistor, and further includes a pair of transistors connected in series to each other by an interconnection node. The interconnection node is connected to the body terminal of the discharge transistor.

Abstract: A method for implementing one-to-one binary functions defined on the Galois field GF(28) is very useful for forming fast and low power hardware devices regardless of the binary function. The method includes decoding an input byte for generating at least one bit string that contains only one active bit, and logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte. The 256-bit string is then encoded in a byte for obtaining the output byte.

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: A pointing and control device for a computer system, the device having a body that can be maneuvered by a user; and an inertial sensor fixed to the body for supplying first signals correlated to the orientation of the body with respect to a gravitational field acting on the inertial sensor. The device moreover includes a magnetometer fixed to the body for supplying second signals correlated to the orientation of the body with respect to the Earth's magnetic field acting on the magnetometer and processing modules for determining an orientation of the body in an absolute reference system, fixed with respect to the Earth's magnetic field and gravitational field on the basis of the first signals and second signals.