Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidically isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract: A device for controlling an electroluminescent matrix display by successive selection of its lines, including a column control circuit having circuitry capable of placing, at the beginning of the selection of a line, the display column at a precharge voltage based on the operating voltage of the previous line, the column control circuit also having circuitry capable of modifying the precharge voltage according to the difference between luminance instructions of the previous line and those of the selected line.

Abstract: An embodiment of an arrangement for detecting sequences of digitally modulated symbols from multiple sources. The arrangement identifies a suitable set of candidate values for at least one transmitted sequence of symbols and determines for each candidate value a set of sequences of transmitted symbols. The arrangement estimates at least one further set of sequence of transmitted symbols, calculates a metric for each sequence of transmitted symbols and selects the sequence that maximizes the metric. At the end, a-posteriori bit soft output information for the selected sequence is calculated from the metrics for said sequences. Generally, these calculations are base on the information coming from a channel state information matrix and a-priori information on said modulated symbols from a second module, such as a forward error correction code decoder.

Abstract: An embodiment of a wireless galvanic isolator device is formed by a transmitter circuit, a receiver circuit, and a wireless coupling structure, arranged between the transmitter circuit and the receiver circuit. The wireless coupling structure is formed by a pair of antennas each arranged on an own die and integrated together with the respective transmitter and receiver circuit. The two dice may be arranged adjacent to each other in a planar configuration or arranged on top of each other and bonded together.

Abstract: A network, such as a network on chip, includes a plurality of levels of switches organized in a hierarchy. The connections between the switches are constituted by connections which are able to transport packets of information in opposite directions in such a way that one switch, or one process associated thereto, can send or receive packets in the framework of the network along one and the same path, constituted by an ascending stretch, in which the packet goes up the network hierarchy as far as a root switch common to the source and to the destination, and a descending stretch in which the packet goes down the network hierarchy towards the destination. A routing logic is provided, configured for defining the routing path in a non-adaptive way, selecting the ascending stretch according to the source and the descending stretch according to the destination, irrespective of the traffic of the packets.

Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.

Abstract: A device for shifting the level of a first signal of relatively low amplitude which is a function of a first supply voltage to a second signal of relatively high amplitude which is a function of a second supply voltage, comprising, between a first terminal of application of the second supply voltage and a first input terminal, a branch of two transistors of opposite types in series, having their junction point defining an output terminal, the respective control terminals of the transistors being connected to terminals of application of relatively high and low bias voltages by first resistive elements, a second input terminal, receiving the inverse of the signal applied on the first terminal, being connected to each of the control terminals of the transistors by first capacitive elements and the first input terminal being connected to each of the terminals of application of the bias voltages by second capacitive elements in series with second resistive elements.

Abstract: The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter (22) arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (24-26) arranged to generate a corrected count value by determining the state of said input signal at the start time (70) and end time (72) of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.

Abstract: A charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columnar structures of a second conductivity type, which extend through the epitaxial layer. A first surface region of the second conductivity type extends along the surface of the epitaxial layer on top of, and in contact with, the columns, and a second surface region of the first conductivity type extends within the first surface region, and also faces the surface of the epitaxial layer. The columns extend at a distance from one another from the first surface region so as to delimit between them an epitaxial portion that defines a current path so as to reduce the on-resistivity of the device.

Abstract: Energy recovery during recirculation phases of the phase windings of a multiphase spindle motor is increased when all the MOSFETs of the output bridge stage associated therewith are turned off (tristated) for charging a hold capacitor. This is accomplished by allowing the recirculation of the motor currents through the same MOSFETs of the output bridge stage that are turned on during the current recirculation phases. Recirculation of the currents and the charging of the hold capacitor takes place through fully saturated power MOSFETs.

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for a car radio. In an embodiment, the synchronous serial digital interface for at least dual radio receiver systems includes a master device and a slave device. The dual radio receiver system has an intermediate frequency. The master device and the slave device exchange data in a bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supplies a synchronization signal to the slave device. The synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitudes at the other frequencies of the synchronization signal.

Abstract: In a pedometer device for detecting and counting steps of a user on foot, an accelerometer sensor detects a vertical acceleration generated during the step. A processing unit, connected to the accelerometer sensor, processes an acceleration signal relating to the acceleration in order to detect the occurrence of a step, and in particular compares the acceleration signal with a first reference threshold. The processing unit automatically adapts the first reference threshold as a function of the acceleration signal. In particular, the processing unit modifies the first reference threshold as a function of an envelope of the amplitude of the acceleration signal.

Abstract: A reduced hardware control circuit device includes a current loop for broad band Hard Disk Drive applications. The current loop detects the value of the current flowing on the coils of a voice coil electric motor incorporated in the Hard Disk Drive. A sensing resistance is connected in series with the motor and at least a driving driver for a relative motor coil. Advantageously the current loop is a transconductance loop with a first transconductance amplifier associated with the sensing resistance. A second transconductance amplifier is provided for fixing the current value to be applied to the motor. The circuit device advantageously is deprived of a local compensation in correspondence with the first transconductance amplifier.

Abstract: A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.

Abstract: An oversampling electromechanical modulator, including a micro-electromechanical sensor which has a first sensing capacitance and a second sensing capacitance and supplies an analog quantity correlated to the first sensing capacitance and to the second sensing capacitance; a converter stage, which supplies a first numeric signal and a second numeric signal that are correlated to the analog quantity; and a first feedback control circuit for controlling the micro-electromechanical sensor, which supplies an electrical actuation quantity correlated to the second numeric signal.

Abstract: A micro-electro-mechanical device formed by a body of semiconductor material having a thickness and defining a mobile part and a fixed part. The mobile part is formed by a mobile platform, supporting arms extending from the mobile platform to the fixed part, and by mobile electrodes fixed to the mobile platform. The fixed part has fixed electrodes facing the mobile electrodes, a first biasing region fixed to the fixed electrodes, a second biasing region fixed to the supporting arms, and an insulation region of insulating material extending through the entire thickness of the body. The insulation region insulates electrically at least one between the first and the second biasing regions from the rest of the fixed part.

Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

Abstract: A method and circuit for displaying an image by activation of pixels of an array screen based on an image stored in digital form in memory point rows of a frame memory, having a stand-by mode that provides, at a frequency proportional to the display frequency, a cyclic succession of offset values; and for each row address of the frame memory, activating pixels of a screen line associated with said address offset by a same offset value based on the read states of the row associated with the address, and/or activating pixels of a screen line associated with the row address based on the read states of the frame memory row associated with the address offset by a same offset value.

Abstract: A device processes a received radio signal. Circuitry formulates voltage samples of the radio signal. Analog processing of those samples is performed. Then, digital processing is performed on the output of the analog processing. The circuitry for formulating voltage samples is configured to ensure a processing of the samples prior to the digital processing.

Abstract: A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.