Patents Assigned to STMicroelectronics SA.A.
  • SBFET TRANSISTOR AND CORRESPONDING FABRICATION PROCESS
    Publication number: 20170162672
    Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.
    Type: Application
    Filed: December 8, 2016
    Publication date: June 8, 2017
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Louis HUTIN, Julien BORREL, Yves MORAND, Fabrice NEMOUCHI
  • Integrated hall effect sensor with a biased buried electrode
    Patent number: 9671473
    Abstract: The generation of a Hall voltage within a semiconductor film of an integrated Hall effect sensor uses the flow of a current within the semiconductor film when subjected to a magnetic field. The film is disposed on top of an insulating layer, referred to as buried layer, which is itself disposed on top of a carrier substrate containing a buried electrode that is situated under the insulating layer. A biasing voltage is applied to the buried electrode.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 6, 2017
    Assignee: STMicroelectronics SA
    Inventors: Severin Trochut, Eric Remond
  • Process for fabricating an integrated circuit comprising at least one coplanar waveguide
    Patent number: 9673088
    Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 6, 2017
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Method for manufacturing a fin MOS transistor
    Patent number: 9673329
    Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 6, 2017
    Assignees: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec, Maud Vinet
  • PLASMONIC FILTER
    Publication number: 20170153367
    Abstract: An infrared high-pass plasmonic filter includes a copper layer interposed between two layers of a dielectric material. An array of patterned openings extend through the copper layer and are filled with the dielectric material. Each patterned opening is in the shape of a greek cross, with the arms of adjacent patterns being collinear. A ratio of the width to the length of each arm is in the range from 0.3 to 0.6, and the distance separating the opposite ends of arms of adjacent patterns is shorter than 10 nm.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 1, 2017
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Romain Girard Desprolet, Sandrine Lhostis, Salim Boutami
  • On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges
    Patent number: 9666577
    Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 30, 2017
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National De La Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • ELECTRONIC DEVICE, IN PARTICULAR FOR PROTECTION AGAINST OVERVOLTAGES
    Publication number: 20170148780
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Application
    Filed: April 12, 2016
    Publication date: May 25, 2017
    Applicant: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Electronic chip comprising transistors with front and back gates
    Patent number: 9660034
    Abstract: An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 23, 2017
    Assignee: STMicroelectronics SA
    Inventor: Philippe Galy
  • On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges
    Patent number: 9653476
    Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 16, 2017
    Assignees: Commissariate a l'energie atomique et aux energies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Method for manufacturing BAW resonators on a semiconductor wafer
    Patent number: 9647625
    Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 9, 2017
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: David Petit, Sylvain Joblot, Pierre Bar, Jean-Francois Carpentier, Pierre Dautriche
  • Process for producing a microfluidic circuit within a three-dimensional integrated structure, and corresponding structure
    Patent number: 9646914
    Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 9, 2017
    Assignee: STMicroelectronics SA
    Inventors: Pierre Bar, Perceval Coudrain
  • Wireless device pairing
    Patent number: 9647724
    Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 9, 2017
    Assignees: STMicroelectronics SA, STMicroeletronics (Crolles 2) SAS
    Inventors: Pascal Urard, Christophe Regnier, Daniel Gloria, Olivier Hinsinger, Philippe Cavenel, Lionel Balme
  • Electro-optic (E/O) device with an E/O amplitude modulator and associated methods
    Patent number: 9645469
    Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 9, 2017
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Patrick Lemaitre, Jean-Francois Carpentier, Charles Baudot, Jean-Robert Manouvrier
  • Electronic device with hollowed-out rear plate
    Patent number: 9648724
    Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: May 9, 2017
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Nicolas Hotellier, François Guyader, Vincent Fiori, Richard Fournel, Frédéric Gianesello
  • Bipolar transistor manufacturing method
    Patent number: 9640631
    Abstract: A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 2, 2017
    Assignee: STMicroelectronics SA
    Inventors: Alain Chantre, Pascal Chevalier, Gregory Avenier
  • High quantum efficiency photodetector
    Patent number: 9640704
    Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1?n2 and n3?n4 have opposite signs.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 2, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics SA
    Inventors: Laurent Frey, Michel Marty
  • Method for determining a three-dimensional stress field of an object, an integrated structure in particular, and corresponding system
    Patent number: 9638589
    Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 2, 2017
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Vincent Fiori, Pierre Bar, Sébastien Gallois-Garreignot
  • Electronic device for a radiofrequency signal reception chain, comprising a low-noise transimpedance amplifier stage
    Patent number: 9641143
    Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 2, 2017
    Assignee: STMicroelectronics SA
    Inventor: Laurent Chabert
  • Optical modulator with automatic bias correction
    Patent number: 9638940
    Abstract: An optical modulator uses an optoelectronic phase comparator configured to provide, in the form of an electrical signal, a measure of a phase difference between two optical waves. The phase comparator includes an optical directional coupler having two coupled channels respectively defining two optical inputs for receiving the two optical waves to be compared. Two photodiodes are configured to respectively receive the optical output powers of the two channels of the directional coupler. An electrical circuit is configured to supply, as a measure of the optical phase shift, an electrical signal proportional to the difference between the electrical signals produced by the two photodiodes.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS SA
    Inventor: Jean-Robert Manouvrier
  • METHOD FOR MANUFACTURE OF A SEMICONDUCTOR WAFER SUITABLE FOR THE MANUFACTURE OF AN SOI SUBSTRATE, AND SOI SUBSTRATE WAFER THUS OBTAINED
    Publication number: 20170103913
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Application
    Filed: March 27, 2015
    Publication date: April 13, 2017
    Applicant: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen