Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

Abstract: A system for detecting a presence in an environment to be monitored includes an electrostatic charge variation sensor, a vibration sensor, and an environmental pressure sensor. A processing unit is configured to acquire, from the electrostatic charge variation sensor, an electrostatic charge variation signal, and detect in the electrostatic charge variation signal, first signal characteristics indicative of the presence of a subject in the environment to be monitored. The processing unit further validates the detection of presence of the subject using the vibration and pressure signals provided by the other sensors.

Abstract: An optical sensor package includes an emitter die mounted to an upper surface of a package substrate. A sensor die is mounted to the upper surface of the package substrate using a film on die (FOD) adhesive layer that extends over the upper surface and encapsulates the emitter die. The sensor die is positioned in a stacked relationship with respect to the emitter die such that a light channel region which extends through the sensor die is optically aligned with the emitter die. Light emitted by the emitter die passes through the light channel region of the sensor die. The emitter die and the sensor die are each electrically coupled to the package substrate.

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: Provided is a device comprising a frequency demodulator and an amplitude demodulator. The device is configured to use, in a first mode, both the frequency demodulator and the amplitude demodulator in parallel and to activate a radio frequency identification (RFID) card mode or a Qi charger mode based on results provided by said demodulators.

Abstract: A method of performing an electro-thermo simulation includes defining a non-linear heat diffusion problem for at least a portion of a semiconductor device to be modeled, performing a finite volume discretization of the non-linear heat diffusion problem, reformulating a non-linear term of the discretized non-linear heat diffusion problem to decrease dimensions thereof, performing a hyper reduction of the reformulated non-linear term, and recovering the non-linear heat diffusion problem for the portion of the semiconductor device, and manufacturing the modeled semiconductor device.

Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.

Abstract: A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.

Abstract: An imaging sensor includes a pixel array containing photodiodes, the photodiodes being isolated from one another by full thickness deep trench isolations. Row control circuitry controls which rows of the pixel array operate in an imaging mode and which rows of the pixel array operate in an energy harvesting mode, on a row by row basis. Switch circuitry selectively connects different groups of photodiodes in rows operating in the energy harvesting mode into forward biased series configurations between a voltage output line and a ground line, or into forward biased parallel configurations between the voltage output line and the ground line.

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

Abstract: In accordance with an embodiment, a method for determining an overall memory size of a global memory area configured to store input data and output data of each layer of a neural network includes: for each current layer of the neural network after a first layer, determining a pair of elementary memory areas based on each preceding elementary memory area associated with a preceding layer, wherein: the two elementary memory areas of the pair of elementary memory areas respectively have two elementary memory sizes, each of the two elementary memory areas are configured to store input data and output data of the current layer of the neural network, the output data is respectively stored in two different locations, and the overall memory size of the global memory area corresponds to a smallest elementary memory size at an output of the last layer of the neural network.

Abstract: The present disclosure relates to a method and device for performing an elliptic curve cryptography computation comprising: twisting, by a first device based on a first index of quadratic or higher order twist (d), a first point (P?KB) on a first elliptic curve over a further elliptic curve twisted with respect to the first elliptic curve to generate a twisted key (PKB); transmitting the twisted key (PKB) to a further device; receiving, from the further device, a return value (ShS) generated based on the twisted key (PKB); and twisting, by the first device based on the first index of quadratic or higher order twist (d), the return value (ShS) over the first elliptic curve to generate a result (ShS?) of the ECC computation.

Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

Abstract: A method includes emitting, by a single sensor of a device, a signal into a region; receiving, by the single sensor, a reflected signal; and detecting motion in a detection cone comprising a central axis based on the reflected signal, wherein detecting motion comprises detecting a first type of motion from a first position to a second position, and detecting a second type of motion from the second position to the first position.

Abstract: In an embodiment, a method of managing an output power delivered by an antenna of a NFC apparatus includes: providing a matching circuit with a first tuning capacitive network coupled in series between a NFC controller and the antenna and with a second tuning capacitive network coupled to the NFC controller and the antenna and to a reference terminal, wherein the first or second tuning capacitive network has a variable capacitive value; determining tuning capacitive values of the first tuning capacitive networks to adjust a delivered output power at a desired level; and setting the tuning capacitive values of the first tuning capacitive network to the tuning capacitive values.

Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

Abstract: A method, for determining the real distance separating an object and an optical detection system, includes, from several so-called reported distances respectively less than or equal to individual reference distances dependent respectively on modulation frequencies: in a first step, determining an initial deviation coefficient between the reported distances and incrementing the smallest of the reported distances with the corresponding individual reference distance; then in a second step, determining a current deviation coefficient between the current distances obtained in the preceding step and incrementing the smallest of the current distances with the corresponding individual reference distance; and in a third step, repeating the second step until all the current distances exceed a common reference distance greater than the individual reference distances.

Abstract: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.