Abstract: A support substrate has a mounting face with a metal heat transfer layer. Holes are provided to extend at least partially through the metal heat transfer layer. Metal heat transfer elements are disposed in the holes of the metal heat transfer layer of the support substrate. An electronic integrated circuit (IC) chip has a rear face that is fixed to the mounting face of the support substrate via a layer of adhesive material. The metal heat transfer elements disposed in the holes of the metal layer of the support substrate extend to protrude, relative to the mounting face of the support substrate, into the layer of adhesive material.

Abstract: An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.

Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

Abstract: A MEMS actuator includes a mobile mass suspended over a substrate in a first direction and extending in a plane that defines a second direction and a third direction perpendicular thereto. Elastic elements arranged between the substrate and the mobile mass have a first compliance in a direction parallel to the first direction that is lower than a second compliance in a direction parallel to the second direction. Piezoelectric actuation structures have a portion fixed with respect to the substrate and a portion that deforms in the first direction in response to an actuation voltage. Movement-transformation structures coupled to the piezoelectric actuation structures include an elastic movement-conversion structure arranged between the piezoelectric actuation structures and the mobile mass. The elastic movement-conversion structure is compliant in a plane formed by the first and second directions and has first and second principal axes of inertia transverse to the first and second directions.

Abstract: A system on chip includes a monitoring circuit that detects an anomalous behavior of the system on chip. The monitoring circuit compares a behavior of the system on chip to at least one reference parameter representing the anomalous behavior of the system. Using this comparison, the anomalous behavior of the system on chip is detected. An interrupt is the issued in response to the detected anomalous behavior of the system on chip.

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

Abstract: An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Abstract: An embodiment apparatus comprises a switching-type output power stage, a modulator circuit configured for carrying out a pulse-width modulation and converting an electrical input signal into an input signal pulsed between two electrical levels, having a mean value proportional to the amplitude of the input signal, and a circuit arrangement for controlling saturation of an output signal supplied by the switching-type output power stage. The circuit arrangement comprises a pulse-remodulator circuit, between the output of the modulator circuit and the input of the switching-type output power stage, that is configured for supplying, as a driving signal to the switching-type output power stage, a respective modulated signal pulsed between two electrical levels, measuring a pulse width as pulse time interval elapsing between two consecutive pulsed-signal edges of the pulsed input signal, and, if the measurement indicates that the latter is below a given minimum value, remodulating the pulsed input signal.

Abstract: A capacitive element has its terminals coupled together by two thyristors electrically in antiparallel. The discharge of the capacitive element is controlled by the application of a gate current to one thyristor of the two thyristors which is in a reverse-biased state in response to a voltage stored across the terminals of the capacitive element. The reverse-biased thyristor responds to the applied gate current by passing a leakage current to discharge the stored voltage.

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

Abstract: The present disclosure relates to a circuit including an input terminal configured to receive a first signal at a first frequency; a demodulation chain connected to the input terminal and including a low-noise amplifier having an input coupled to the terminal; a controllable variable impedance connected between a first node and a node configured to receive a reference potential, the first node being connected to the input terminal and/or to the amplifier input; and a current source configured to deliver a current at the first frequency to the first node.

Abstract: A microelectromechanical mirror device has, in a die of semiconductor material: a fixed structure defining a cavity; a tiltable structure carrying a reflecting region elastically suspended above the cavity; at least a first pair of driving arms coupled to the tiltable structure and carrying respective piezoelectric material regions which may be biased to cause a rotation thereof around at least one rotation axis; elastic suspension elements coupling the tiltable structure elastically to the fixed structure and which are stiff with respect to movements out of the horizontal plane and yielding with respect to torsion; and a piezoresistive sensor configured to provide a detection signal indicative of the rotation of the tiltable structure. At least one test structure is integrated in the die to provide a calibration signal indicative of a sensitivity variation of the piezoresistive sensor in order to calibrate the detection signal.

Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.

Abstract: A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.