Patents Assigned to STMicroelectronics
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Publication number: 20220130454Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.Type: ApplicationFiled: September 23, 2021Publication date: April 28, 2022Applicant: STMicroelectronics International N.V.Inventor: Kedar Janardan DHORI
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Publication number: 20220131215Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Applicant: STMicroelectronics (Tours) SASInventor: Vincent JARRY
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Publication number: 20220130728Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
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Publication number: 20220130990Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Applicant: STMicroelectronics S.r.l.Inventors: Ferdinando IUCOLANO, Alfonso PATTI
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Publication number: 20220131005Abstract: An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.Type: ApplicationFiled: October 19, 2021Publication date: April 28, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Benoit FROMENT, Thomas CABOUT
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Patent number: 11314852Abstract: A method can be used for the generation of personalized Profile Package data in integrate circuit cards. A table includes data records corresponding to subscriptions to be generated. Each record includes personalization fields to store different types of personalization values. For a given subscription, a file for the Profile Package is in an ASCII format and includes fields to be personalized corresponding to one or more of the fields to store different types of personalization values. The file for the Profile Package in the ASCII format is converted into a hexadecimal code. An offset table is calculated for the given subscription indicating for each field to be personalized a corresponding offset in the hexadecimal profile. The personalization values from the personalization fields are substituted in the corresponding personalization fields to be personalized.Type: GrantFiled: May 16, 2019Date of Patent: April 26, 2022Assignee: STMicroelectronics S.r.l.Inventors: Marco Alfarano, Giancarlo Pasquariello
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Patent number: 11312238Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.Type: GrantFiled: June 5, 2020Date of Patent: April 26, 2022Assignee: STMicroelectronics S.r.l.Inventors: Orazio Pennisi, Valerio Bendotti, Vittorio D'Angelo, Paolo Turbanti
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Publication number: 20220122657Abstract: An integrated circuit includes a memory array. The memory array includes a plurality of bitlines. The bitlines are each coupled to a respective local I/O circuit. All of the local I/O circuits are coupled to a global I/O circuit. Each local I/O circuit includes a first sensing stage for reading data from the memory cell. The global I/O circuit includes a second sensing stage for reading data from the memory cell.Type: ApplicationFiled: October 5, 2021Publication date: April 21, 2022Applicant: STMicroelectronics International N.V.Inventor: Kedar Janardan DHORI
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Publication number: 20220118480Abstract: A PMUT device includes a membrane element extending perpendicularly to a first direction and configured to generate and receive ultrasonic waves by oscillating about an equilibrium position. At least two piezoelectric elements are included, with each one located over the membrane element along the first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. The membrane element has a lobed shape along a plane perpendicular to the first direction, with the lobed shape including at least two lobes. The membrane element includes for each piezoelectric member a corresponding membrane portion including a corresponding lobe, with each piezoelectric member being located over its corresponding membrane portion.Type: ApplicationFiled: October 8, 2021Publication date: April 21, 2022Applicant: STMicroelectronics S.r.l.Inventors: Domenico GIUSTI, Fabio QUAGLIA, Marco FERRERA
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Publication number: 20220121913Abstract: An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.Type: ApplicationFiled: October 12, 2021Publication date: April 21, 2022Applicant: STMicroelectronics SAInventors: Valerian CINCON, Philippe GALY
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Publication number: 20220120589Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: STMicroelectronics (Rousset) SASInventor: Pascal FORNARA
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Publication number: 20220123699Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Applicant: STMicroelectronics International N.V.Inventor: Prashant Singh
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Publication number: 20220123119Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Christian RIVERO, Philippe BOIVIN, Francois TAILLIET, Roberto SIMOLA
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Publication number: 20220122941Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.Type: ApplicationFiled: September 23, 2021Publication date: April 21, 2022Applicant: STMicroelectronics PTE LTDInventors: Chun Yi TENG, David GANI
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Publication number: 20220119246Abstract: A PMUT device includes a membrane element adapted to generate and receive ultrasonic waves by oscillating, about an equilibrium position, at a corresponding resonance frequency. A piezoelectric element is located over the membrane element along a first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. A damper is configured to reduce free oscillations of the membrane element, and the damper includes a damper cavity surrounding the membrane element, and a polymeric member having at least a portion over the damper cavity along the first direction.Type: ApplicationFiled: October 8, 2021Publication date: April 21, 2022Applicant: STMicroelectronics S.r.l.Inventors: Domenico GIUSTI, Marco FERRERA, Fabio QUAGLIA
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Publication number: 20220123105Abstract: An electrode structure includes a pad of conductive material, and a conductive strip having a first end physically and electrically coupled to the pad. The pad includes an annular element internally defining a through opening. The first end of the conductive strip is physically and electrically coupled to the annular element by a transition region so that, when the conductive strip undergoes expansion by the thermal effect, a stress spreads from the conductive strip to the annular element by the transition region.Type: ApplicationFiled: October 5, 2021Publication date: April 21, 2022Applicant: STMicroelectronics S.r.l.Inventors: Fabrizio CERINI, Silvia ADORNO, Dario PACI, Marco SALINA
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Publication number: 20220119245Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.Type: ApplicationFiled: October 12, 2021Publication date: April 21, 2022Applicant: STMicroelectronics S.r.l.Inventors: Nicolo' BONI, Lorenzo VINCIGUERRA, Roberto CARMINATI, Massimiliano MERLI
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Publication number: 20220123650Abstract: A circuit includes two thyristors coupled in anti-series. An AC capacitor has first and second electrodes respectively coupled to two different electrodes of the two thyristors. The first and second electrodes are coupled to receive an AC voltage. A control circuit detects discontinuance of application of the AC voltage to the AC capacitor and in response thereto simultaneously applies same gate currents to the two thyristors. A current path through the two thyristors (one passing current in forward mode and the other in reverse mode) discharges a residual voltage stored on the AC capacitor.Type: ApplicationFiled: January 4, 2022Publication date: April 21, 2022Applicant: STMicroelectronics LTDInventor: Laurent GONTHIER
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Publication number: 20220122969Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.Type: ApplicationFiled: October 18, 2021Publication date: April 21, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Edoardo BREZZA, Alexis GAUTHIER
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Patent number: 11308979Abstract: A method and apparatus for classifying a spatial environment as open or enclosed are provided. In the method and apparatus, one or more microphones detect ambient sound in a spatial environment and output an audio signal representative of the ambient sound. A processor determines a spatial environment impulse response (SEIR) for the audio signal and extracts one or more features of the SEIR. The processor classifies the spatial environment as open or enclosed based on the one or more features of the SEIR.Type: GrantFiled: January 26, 2021Date of Patent: April 19, 2022Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl
