Abstract: A leadframe includes a die pad and electrically conductive leads arranged peripherally of the die pad. A semiconductor die is mounted to the die pad. The die is electrically coupled to the electrically conductive leads using an electrical coupling member applied onto the semiconductor die. The electrical coupling member includes a planar body configured to cover the semiconductor die and the electrically conductive leads. The planar body of the electrical coupling member includes strip-like, electrically conductive formations embedded in an electrically insulating material. Each strip-like, electrically conductive formation has a first end configured to contact the semiconductor die and a second end configured to contact the electrically conductive lead.

Abstract: A device and method for manufacturing a device comprising two semiconductor dice. The device is formed by a first die and a second die. The first die is of semiconductor material and integrates electronic components. The second die has a main surface, forms patterned structures, and is bonded to the first die. Internal electrical coupling structures electrically couple the main surface of the first die to the second die. External connection regions extend on the main surface of the first die. A package packages the first die, the second die and the internal electrical coupling structures and partially surrounds the external connection regions, the external connection regions partially protruding from the package.

Abstract: A method for manufacturing a PMUT device including a piezoelectric element located at a membrane element is provided. The method includes receiving a silicon on insulator substrate having a first silicon layer, an oxide layer, and a second silicon layer. Portions of a first surface of the second silicon layer are exposed by removing exposed side portions of the first silicon layer and corresponding portions of the oxide layer, and a central portion including the remaining portions of the first silicon layer and of the oxide layer is defined. Anchor portions for the membrane element are formed at the exposed portions of the first surface of the second silicon layer. The piezoelectric element is formed above the central portion, and the membrane element is defined by selectively removing the second layer and removing the remaining portion of the oxide from under the remaining portion of the first silicon layer.

Abstract: A method includes counting a first set of photons having times of flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having times of flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.

Abstract: Embodiments of a Coriolis-force-based flow sensing device and embodiments of methods for manufacturing embodiments of the Coriolis-force-based flow sensing device, comprising the steps of: forming a driving electrode; forming, on the driving electrode, a first sacrificial region; forming, on the first sacrificial region, a first structural portion with a second sacrificial region buried therein; forming openings for selectively etching the second sacrificial region; forming, within the openings, a porous layer having pores; removing the second sacrificial region through the pores of the porous layer, forming a buried channel; growing, on the porous layer and not within the buried channel, a second structural portion that forms, with the first structural region, a structural body; selectively removing the first sacrificial region thus suspending the structural body on the driving electrode.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.

Abstract: A sensor package includes a packaging formed by a package bottom, first and second sidewalls extending upwardly from first and second opposite sides of the package bottom, and third and fourth sidewalls extending upwardly from third and fourth opposite sides of the package bottom, the sidewalls and package bottom defining a cavity. An integrated circuit is attached to the package bottom. A plate extends between two of the sidewalls within the cavity and is spaced apart from the package bottom. Sensors are attached to a top surface of the plate on opposite sides of an opening. Wire bondings electrically connect pads on a top face of the sensor to corresponding pads on a top face of the integrated circuit, for example by passing through the opening in the plate or passing past a side end of the plate. A lid extends across and between the sidewalls to close the cavity.

Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.

Abstract: The present disclosure concerns a voltage regulation circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: between a first terminal and a second terminal, a first resistor and a first d-mode type HEMT transistor; and between the first terminal and the third terminal, a second d-mode type HEMT transistor; wherein the midpoint between the first resistor and the first transistor is coupled to the gates of the first and second transistors.

Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

Abstract: A method corrects an ionospheric error affecting pseudo-range measurements in a GNSS receiver receiving a plurality of satellite signals from a plurality of satellites of the constellation of satellites. The method is performed in a navigation processing procedure performed at a GNSS receiver, receiving pseudo-range measurements previously calculated by the GNSS receiver obtained from a first carrier signal and a second carrier signal in the satellite signals, in particular in GPS bands L1 and L5. The method includes performing a correction procedure of the pseudo-range measurements including applying to the pseudo-range measurements corrections for predictable errors obtaining corrected pseudo-ranges and applying to the corrected pseudo-range measurements a further ionospheric error correction calculation to obtain further ionospheric error correction values.

Abstract: A device includes a memory and cryptographic processing circuitry coupled to the memory. The memory, in operation, stores one or more lookup tables. The cryptographic processing circuitry, in operation, processes masked data and protects the processing of masked data against side channel attacks. The protecting includes applying masked binary logic operations to masked data using lookup tables of the one or more lookup tables.

Abstract: The present disclosure concerns overtemperature protection circuit formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising: a first resistor having a first positive temperature coefficient and being arranged in said gallium nitride layer; and a second resistor having a second temperature coefficient different from the first coefficient.

Abstract: The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm2.

Abstract: An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.

Abstract: The present disclosure concerns an electronic device formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, comprising at least one e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, and an analog circuit for controlling said power transistor.

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.

Abstract: A method for operating an electronic device, including: determining that a touchscreen is in a low frequency display (LFD) mode, determining whether a self-sensing scan was performed in a previous frame of a plurality of frames; after determining, a self-sensing scan was performed in the previous frame, determining a current duration of time corresponding to a current frame based on a previous duration of time corresponding to the previous frame, the previous frame being a frame immediately preceding the current frame; determining, whether the current duration of time is greater than the previous duration of time; and after determining that the current duration is greater than the previous duration, performing a self-sensing scan after the current duration of time, the current duration of time being measured from a beginning of the current frame, the current duration of time having a duration less than a duration of the current frame.

Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.