Abstract: A switching voltage regulator includes a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal based on a difference between the reference voltage and the feedback voltage, and a control module configured to generate a gain control threshold signal based on at least one of the reference voltage and the feedback voltage. The control module may be configured to control a duration of a PWM pulse based on the at least one of the reference voltage and the feedback voltage. The feedback voltage may a regulated output voltage of the switching voltage regulator. The switching voltage regulator may be implemented in an analog or a digital manner.

Abstract: An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

Abstract: A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.

Abstract: A method forms at least one isolation trench in a substrate having an upper surface. The method includes at least: forming, across the substrate thickness, at least one first cavity opened towards the upper surface; totally filling this first cavity with a dielectric material of a first type; forming a second cavity in an upper portion of the first cavity thus filled, said second cavity being opened towards the upper surface and having a substantially concave profile; totally filling this second cavity with a dielectric material of a second type; and leveling the free surface of the trench substantially down to the upper surface level.

Abstract: A photolithography method, including the steps of: S1) depositing, on the upper surface of a wafer, a chemically-amplified resist; S2) exposing the resist to a sensitizing radiation through a mask, to generate acid compounds in the exposed regions; S3) heating the resist, to have the acid compounds react with dissolution-inhibiting groups; and S5) developing the resist; and including, after step S3, a step of neutralization, S4, of the acid compounds which have not reacted at step S3.

Abstract: An embodiment of a testing system for carrying out electrical testing of at least one first through via extending, at least in part, through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the first through via and to electrical-connection elements carried by the first body for electrical connection towards the outside; the first electrical test circuit enables detection of at least one electrical parameter of the first through via through the electrical-connection elements.

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract: A sensing device includes a first current mirror configured to mirror a current flowing through a thermistor, a second current mirror configured to mirror a current flowing through a reference resistor a comparator configured to compare voltages on the thermistor and the resistor, and a counter configured to generate a control signal representative of a temperature difference based on the comparison. The control signal controls a mirroring ratio of the second current mirror. The sensing device may be employed to generate a droop current of a voltage regulator.

Abstract: The disclosure relates to a method for characterizing or measuring a capacitance, comprising: linking the capacitance to a first mid-point of a first capacitive divider bridge, applying to the divider bridge a bias voltage, maintaining the voltage of the first mid-point near a reference voltage, discharging a second mid-point of a second divider bridge in parallel with the first by means of a constant current, and measuring the time for a voltage of the second mid-point to become equal to the voltage of the first mid-point. The disclosure may be applied in particular to the control of a touch screen display.

Abstract: An RF amplifier including first and second branches coupled in parallel between first and second supply voltage terminals, and a differential pair including first and second transistors each having first and second main current terminals, the second main current terminal of the first transistor being coupled by a first capacitor to the first main current terminal of the second transistor, and the second main current terminal of the second transistor being coupled by a second capacitor to the first main current terminal of the first transistor, wherein the first branch includes a first resistor coupled between the first main current terminal to of the first transistor and the second capacitor, and the second branch includes a second resistor; coupled between the first main current terminal of the second transistor and the first capacitor.

Abstract: A switching voltage regulator including a comparison module configured to receive a reference voltage and a feedback voltage and to generate a comparison signal corresponding to a difference between the reference voltage and the feedback voltage, an offset module configured to generate an offset signal based on a number of active phases of the voltage regulator, an adder configured to generate a control signal based on the comparison signal and the offset signal, a plurality of pulse-width-modulated (PWM) power stages, and a control module configured to control the plurality of PWM power stages based at least in part on the control signal generated by the adder.

Abstract: A method for encoding and decoding media signals, includes the operations of generating at a transmitting side multiple descriptions associated to data of the media signals through a downsampling operation performed on the data, and decoding at a receiving side the multiple descriptions for reconstructing the data by merging the multiple descriptions. The operation of generating multiple descriptions further includes the operations of obtaining a spectral representation of the data, including bands associated to different ranges, the bands being obtained by a suitable quantization operation and including at least one highly quantized band, that is subjected to a higher degree of quantization. A scrambling operation is performed on the spectral representation by moving the at least one highly quantized band to a different range, the scrambling operation being performed prior the downsampling operation. In decoding, a descrambling operation is performed before the merging operation on the multiple descriptions.

Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically coupled together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.

Abstract: A resonant dc-dc converter converts dc input voltage to a dc output voltage. The converter includes switching, switching driving, conversion, and disabling circuits. The switching circuit receives the input voltage and generates a square wave voltage oscillating between the input voltage and a low value, at a frequency with a duty cycle. The switching driving circuit drives the switching circuit and includes a timing circuit for setting the frequency and the duty cycle. The timing circuit sets the value of the duty cycle to about 50% when the converter operates in steady state. The conversion circuit generates the output voltage from the square wave voltage based on the frequency and the duty cycle. The disabling circuit temporarily halts the timing circuit after a power on in such a way to temporarily vary the duty cycle of the square wave voltage during a period of the square wave voltage.

Abstract: A method and system by which a base station in a Wireless Regional Area Network (WRAN), and more generally a transceiver in a cognitive radio (CR) system, can communicate with other transceivers to fairly share transmission and reception of scheduled use (“occupancy”) of frames on a single channel within a frame-based, on demand spectrum contention system. The method and system disclose how the base station currently occupying a channel responds to requests from other base stations for an increased share of the frames available in a subsequent superframe of the CR system. The method and system assure fair and efficient access to the transmission channel by a random number based contention process.

Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.

Abstract: A directional anti-aliasing filter circuit includes an input node and an output node, a directional anti-aliasing filter having an input coupled to the input node, an adaptive gain control having an input coupled to an output of the directional anti-aliasing filter, a summer having a first input coupled to an output of the adaptive gain control, a second input coupled to the input node, and an output coupled to the output node, a texture detector for providing a texture adjust signal to the directional anti-aliasing filter and a texture adaptive gain signal to the adaptive gain control, an edge detector for providing an edge direction signal to the directional anti-aliasing filter, and a corner detector for providing a corner adaptive gain signal to the adaptive gain control.

Abstract: A circuit for converting a measured variable capacitance to an output voltage signal includes a charge amplifier circuit selectively coupled to an integrator circuit. The charge amplifier circuit, in one implementation, is configured as a high pass filter. In another implementation, the charge amplifier circuit is configured as a combination high pass and low pass filter. The charge amplifier circuit is selectively coupled to the integrator circuit when the circuit forces a switch in voltage across a measurement capacitor.

Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.

Abstract: The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word.