Abstract: A cell for detecting a disturbance capable of affecting the operation of a processor in which it is integrated, including circuitry for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.

Abstract: A microelectronic device includes a first circuit and a second circuit, coupled to the first circuit for selectively preventing operation of the first circuit when a device temperature is higher than a temperature threshold. The second circuit is provided with a temperature responsive element, thermally coupled to the first circuit for providing a shutdown signal correlated to the device temperature. The temperature responsive element includes a reverse-biased junction element and the shutdown signal is correlated to a reverse leakage current of the reverse-biased junction element.

Abstract: A plurality of planar electrodes (5) in a microchannel (4) is used for separation, lysis and PCR in a chip (10). Cells from a sample are brought to the electrodes (5). Depending on sample properties, phase pattern, frequency and voltage of the electrodes and flow velocity are chosen to trap target cells (16) using DEP, whereas the majority of unwanted cells (17) flushes through. After separation the target cell (16) are lysed while still trapped. Lysis is carried out by applying RF pulses and/or thermally so as to change the dielectric properties of the trapped cells. After lysis, the target cells (16) are amplified within the microchannel (4), so as to obtain separation, lysis and PCR on same chip (1).

Abstract: In the MSN encoded form, the symbols of each block of the present invention define a running digital sum (RDS) value, defined as RDS([a0a1 . . . aN?1])=??i(?1)ai where the symbols ai belong to the set {0, 1} and the sum extends for values of i from 0 to N?1. An encoder is configured to satisfy at least one of the following characteristics: a) blocks of symbols with a given length (L) are used for encoding, wherein RDS=RDS0+4.K, where K is an integer, RDS is the said running digital sum, RDS0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks.

Abstract: A capacitive microsensor formed on a wafer, including a conductive detection area arranged on a first surface or front surface of the wafer; a conductive via crossing the wafer and emerging on said area; and a structure to ensure contact with said via on the second surface or rear surface of the wafer.

Abstract: A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one instruction for exchanging the contents of both memory locations. The microprocessor includes an additional internal register connected to an output of the arithmetic and logic unit, and transfers the contents of a first one of the memory locations to be exchanged into the additional register when executing the instruction set. The microprocessor further transfers the contents of a second one of the memory locations to be exchanged into the first memory location, and transfers the contents of the additional register into the second memory location.

Abstract: A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate 4/6 code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate ? code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to the encoded word for obtaining angular and radial information for the head positioning.

Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal.

Abstract: A coprocessor includes a single multiplication circuit coupled to a computation circuit dedicated to the computation of Y0, with Y0=(X*J0) mod 2k and J0 being defined by the equation ((N*J0)+1) mod 2k=0. A method also computes a modular operation using the circuit for the computation of Y0. The computation circuit computes Y0 on the basis, first, of the k least significant bits of a data element X=S(i−1)+(Ai*B) provided by an accumulator and, second, of the least significant word of N contained in a latch.

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Abstract: A high-precision biasing circuit is provided for a CMOS cascode stage with inductive load and degeneration. The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The biasing circuit includes at least a first MOS replica transistor and a second MOS replica transistor, and two current generators for biasing the first and second MOS replica transistors. A circuit block detects a voltage value on a terminal of the second replica MOS transistor and applies a voltage to a gate terminal of the first replica transistor. Two circuit block implementations include a voltage amplifier and a folded cascode amplifier closed in a shunt feedback. Both implementations allow the threshold voltages of the cascode stage transistors to be tracked, as well as their Early and body effects.

Abstract: A class D amplifier includes an input integrating stage and a modulating stage for modulating the integrated input signal output by the integrating stage. The modulating stage uses as a carrier an alternate waveform of a frequency sufficiently higher than the frequency band of the analog input signal. The modulating stage further outputs a digital signal switching between a positive voltage and a negative voltage, and whose average value represents an amplified replica of the input analog signal. The class D amplifier further includes an output power stage producing an output digital signal. A feedback line including a resistor is connected between the output of the output power stage and an input node of an operational amplifier. The class D amplifier also includes a low-pass filter reconstructing an output analog signal, and a delay stage.

Abstract: An integrated circuit includes a first access pin and a second access pin, and an electronic circuit for trimming a portion of the integrated circuit. The electronic circuit includes a memory element, and a regulation circuit for modifying the memory element. The regulation circuit includes an error amplifier for comparing an output voltage of the portion of the integrated circuit to be trimmed with an internal voltage reference. A comparator includes a first input connected to an output of the error amplifier and to the first access pin. A first switch is connected between the output of the error amplifier and the first input of the comparator. A second comparator includes a first input connected to the second access pin, and an output connected to the first switch for control thereof. A second switch is connected to the output of the error amplifier and to the first access pin.

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.