Abstract: A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.

Abstract: A chassis system for housing a plurality of circuit boards, such as PCI standard bus boards, provides a rack-mountable chassis having an open front side and a motherboard with a plurality of board connectors arranged side-by-side with respect to the front end. The boards are mounted in individual frameworks that facilitate ready installation and removal from the chassis. In particular, the chassis includes a plurality of receiving blocks at the bottom rear of the chassis, aligned with each of the motherboard connectors. The receiving blocks receive pivots mounted on the back of each framework. The framework is inserted into, and removed from the front opening of the chassis in an upwardly pivoted position that clears the motherboard connectors and other obstructions in the chassis. The framework is pivoted into and out of engagement with the motherboard when the pivot is located in the receiving blocks. The chassis can include top-mounted tracks. The tracks receive rollers on the framework.

Abstract: In a fault-tolerant computer system, a primary replica supervisor is interposed between an operating system and a primary replica of an application program being executed by a primary processor. An object-code editor locates calls to the operating system and loops in the application program and inserts instruction sequences that enable the replica supervisor to intercept the calls to the operating system, results returned by the operating system as a result of the calls and asynchronous events delivered by the operating system to the replica. A backup replica supervisor is similarly interposed between an operating system and a backup replica of the application program being executed by a backup processor. The primary replica interacts with an environment.

Abstract: A method of routing a call including a called number in a communications network such as a Public Switched Telephone Network (PSTN), the method including determining if the called number is a network routing number indicating a specific switching node and line associated therewith in the communications network and routing the call within the communications network based on the called number when the called number is a network routing number. Additionally, the method includes identifying a network routing number based on the called number when the called number is not equal to the network routing number and routing the call within the communications network based on the identified network routing number.

Abstract: A fault-isolating digital data processing apparatus includes plural functional units that are interconnected for point-to-point communications by a plurality of buses. The functional units monitor the buses to which they are attached and signal the other units in the event there are bus communication errors. The functional units can simultaneously enter into an error isolation phase, e.g., in response to a bus error signaled by one of the units. During this phase, each unit transmits test data (e.g., predetermined patterns of O's and 1's) onto at least one of its attached buses. The functional units continue to monitor the buses and to signal bus errors while the test data is being transmitted. In addition to signaling bus errors, the functional units can signal unit-level (or "board") faults when they detect fault in their own operation.

Abstract: A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e.g., longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e.g., causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

Abstract: A fault-tolerant computer system comprises a plurality of processing nodes and a plurality of storage nodes interconnected by a network. The processing nodes perform processing operations in connection with user-generated processing requests. The processing nodes, in connection with processing a processing request, generate storage and retrieval requests for transmission to the storage node to enable storage of data thereon and retrieval of data therefrom. The storage nodes store data in at least one replicated partition group comprising a plurality of replicated partitions distributed across the storage nodes. A storage node, on receiving a retrieval request from a processing node provide the requested data to the processing node. In addition, on receiving a storage request from a processing node, a storage node initiates an update operation to update all of the replicated partitions in the replicated partition group.

Abstract: In a fault-tolerant computer system, a primary replica supervisor is interposed between an operating system and a primary replica of an application program being executed by a primary processor. An object-code editor locates calls to the operating system and loops in the application program and inserts instruction sequences that enable the replica supervisor to intercept the calls to the operating system, results returned by the operating system as a result of the calls and asynchronous events delivered by the operating system to the replica. A backup replica supervisor is similarly interposed between an operating system and a backup replica of the application program being executed by a backup processor. The primary replica interacts with an environment.

Abstract: An actively replicated, fault-tolerant database system based on a state machine approach that supports the concurrent execution of multiple transactions requested by a plurality of application clients communicating with the system. The system includes a plurality of database servers for storing system data and an application server layered over each database server for controlling the access to and the manipulation of data stored at the underlying database server. The application servers replicate system data to at least one other database server and coordinate the execution of transactions at each database server to ensure consistent data replicas across the system. More specifically, the application servers administer one of two preselected, novel coordination protocols governing the execution of each database-dependent transaction.

Abstract: A console terminal arrangement is disclosed for use in connection with a fault-tolerant computer system including a plurality of processing modules, at least some of the processing modules including an operator input/output interface for receiving operator input from an operator input device and operator display output on an operator display device. The console terminal arrangement facilitates management of all of the processing modules by a single operator from a single location. The arrangement includes a console terminal and a plurality of processing module interfaces interconnected by a network. The console terminal includes an operator input device and an operator display device, and generates operator input messages including processing module management information generated by the operator input device in response to inputs provided by an operator and an address identifying one of the processing modules to be managed by the console terminal.

Abstract: A digital data processing device includes a bus for transmitting signals (e.g., data and/or address information) between plural functional units (e.g., a central processing unit and a peripheral controller). A first such unit includes first and second processing sections that concurrently apply to the bus complementary portions of like information signals (e.g., longwords containing data). A fault detection element reads the resultant signal from the bus and compares it with at least portions of the corresponding signals originally generated by the processing sections themselves. If there is discrepancy, the fault-detector signals a fault, e.g., causing the unit to be taken off-line. By use of a redundant unit, processing can continue for fault-tolerant operation.

Abstract: A telephone network includes switches which are capable of mapping between subscriber numbers, which are owned by the subscriber, and provider numbers, which define the physical location of the switch at which the subscriber is connected, in order to provide portability of telephone numbers. Switches which are capable of porting telephone numbers may access a database to look-up a provider number based on a subscriber number and look-up a subscriber number based on a provider number. The subscriber number of the called party is translated to a provider number in order to define the physical location of the switch supporting the called party. The provider number of the calling party is translated to a subscriber number to support caller ID. The database for maintaining information on translating subscriber numbers and provider numbers, and other data, such as call forwarding and switch configurations, may be accessed from a central database and cached locally to the switches.

Abstract: A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.

Abstract: A clock signal generation arrangement for generating clocking signals for use in a fault-tolerant computer system generates a timing signal in response to a common clock signal. The clock signal generation arrangement comprises a system clock signal generator and a clock signal recovery circuit interconnected by a plurality of clock signal transfer lines. The system clock signal generator generates, in response to a common clock signal, a plurality of system clock signals preferably of uniform frequency and phase for transmission over a like plurality of clock signal transfer lines. The clock signal recovery circuit receives the system clock signals from the clock signal transfer lines and generates a unitary timing signal. The clock signal recovery circuit includes a voting circuit, a latch circuit and a latch control circuit. The voting circuit generates a voted clock signal having signal transitions that are generally aligned with transitions of a majority of the system clock signals.

Abstract: A bus device (10) the communicates with other bus devices (12, 13) on a communication channel (14) that includes a plurality of duplicated information buses (16, 17) selectively assumes bus-selection states in which it uses information from one or the other of the buses (16, 17). It also monitors the buses (16, 17) for errors in the information that the buses (16, 17) carry, and it broadcasts an error signal over other lines (18) of the communications channel (14) in response to detection of such an error, but only if an error occurs in information on the bus that its current bus-selection state designates. On the other hand, when an error-broadcast signal indicating an error on either bus in the information transmitted by that device (10) appears on the bus, that bus device (10) retransmits the information, regardless of that device's current bus-selection state. Inconsistent operation phasing among bus devices that have assumed different bus-selection states is thereby avoided.

Abstract: A clock switching circuit switches between clock signals generated by a local clock unit and those generated by a-system clock unit when disabling, and then subsequently enabling, the system clock unit. The clock switching circuit includes a plurality-of switching circuits that are arranged and configured to switch between the system and local clock units so as to provide a substantially uninterrupted stream of clock signals to selected components of a fault-tolerant computer system. This arrangement ensures that information stored on the selected components is not lost during disablement of the system clock unit.

Abstract: A digital data processing apparatus has two functional units (e.g., a host processing section and a peripheral device) and a controller for transferring information therebetween. The first functional unit generates a send message descriptor block ("MDB") signal specifying one or more addresses in an associated local memory from which data is to be transferred. The second functional unit generates a receive MDB signal specifying one or more locations in its associated local memory to which data is to be transferred. The controller matches send and receive MDB signals, particularly, those specifying the same logical or virtual channel. Once a match is found, the controller transfers data between the respective memory locations of the first and second functional units. A controller as described above transfers data between the host and peripheral processors by directly accessing data in their respective "memory spaces.

Abstract: A fault-tolerant digital data processor includes three identical logic CPU boards connected to a voting bus and a system bus. The three boards are initially designated as a master board, a slave board 0 and a slave board 1. The master board drives the system bus and the two slave boards serve as backups in case the master breaks. The master board issues signals, at different instances with the aid of multiplexing, to the slave boards. On the slave boards, corresponding signals are compared and the result is broadcast to all three boards. When all three boards are compared equal, the master board remains as master. If there is a miscompare between one slave board and the master but not between the other slave board and the master, the master board remains master, and the slave board with which the miscompare occurred will be disabled after another miscompare. If a miscompare occurs between the master board and both slave boards, a re-execution of the previous cycle occurs.

Abstract: Fault-tolerant power distribution system for back-mounted hardware in which a backplane arrangement delivers alternative sources of system power in a prioritized pattern to each of a plurality of fault-tolerant electronic cards via a plurality of system slots, each slot including a power port having electrical contacts in a common system pinout, and the cooperating system cards have electrical contacts in the same common system pinout. Any of the system cards can be installed in any system slot and will receive the system power in one of a plurality of fault-tolerant prioritizations.

Abstract: An I/O controller for transferring data between a host processor and one or more I/O units. The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers.