Abstract: An improved method for operating a digital data processing apparatus to provide for fault-tolerant actuation of a functional unit in response to an actuation request includes the steps of: providing the functional unit with a switching section that responds to application of plural switching signals for activating the functional unit; providing first and second processing elements, each normally responding to an actuation request for generating a first set of switching signals, the first set of switching signals including at least one, but not all, of the plural switching signals; outputting the first set of switching signals generated by the first processing element for application to the switching section; synchronizing the first and second processing elements by comparing, with the second processing element, the first set of switching signals generated thereby with those output by the first processing element; generating, after synchronization, with each of the first and second processing elements, a secon

Abstract: A programmable, multi-level interrupt priority encoder which fields interrupts from connected devices, e.g., DMA engine, scanner, and timer, and signals an interrupt value, or priority level, associated with that device. These levels, which may range from zero to seven or more, depending upon the system with which it is applied, are used by the CPU to determine which of the plural interrupting devices to service. Using the encoder of the invention, multiple devices can be set at the same priority level.

Abstract: A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.

Abstract: A state machine in a digital data processor in a UNIX-type operating system environment has state managers associated with the functional units of the data processor for indicating the state of the units; a message handler for, alternately, (a) generating requests for processing event messages indicative of conditions in the processor, that are awaiting processing and (b) generating a request for evaluation of one state manager's maintenance state, limited to transition from one state to another; and a scheduling means responsive to requests from the message handler for selectively processing the event messages, to the passage of time, and to changes of state of state managers, and for scheduling evaluation of a state manager's maintenance state.

Abstract: An improved cabinet for electromagnetic and radio-frequency interference suppression includes an electrical component-mounting rail that includes a series of spring-like conductive projections or tabs internally formed to extend from its surface. The projections are arranged so that, as a component panel is mounted against the rail, the projections contact the panel at a plurality of points, establishing electrical contact between it and the rail. The projections are positioned to maintain distances between radiation-suppressing low impedance contacts of the rail and component which are small in comparison to wavelength of interference generated by the component and, thereby, to attenuate emissions from the cabinet.

Abstract: Digital logic equipment in which two logic elements operate with timing control from a clock element with selected synchronism, includes a failure detecting element which detects the absence of the selected synchronism between the two logic elements even when each is providing otherwise correct logic operation. The apparatus and method enable a digital logic system to follow two redundant digital logic elements so long as they operate in lock step synchronism, and to sense a failure which occurs only in synchronism to disable one of the two logic elements to maintain thereafter uninterrupted operation with the other logic element.

Abstract: A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals from the input/output controller to the peripheral device. A device interface is coupled to the first and second input/output buses and to an associated peripheral device for transferring information between the buses and the associated peripheral device. In normal operation, the device interface applies duplicate information signals synchronously and simultaneously to the input/output buses for transfer to the input/output controller. The device interface also receives, in the absence of fault, duplicative information signal synchronously and simultaneously from the first and second input/output buses.

Abstract: A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Abstract: A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses.

Abstract: A fault-tolerant digital data processing system comprises at least a first peripheral controller communicating with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals. The first peripheral controller includes a first device interface element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The first device interface element also receives, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses. A second peripheral controller is coupled to the peripheral device bus for receiving the first and second input signals identically with the first peripheral controller.

Abstract: A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Abstract: Computer timing apparatus enables two clock elements to produce a single stream of timing pulses, without interruption, when both elements are operating normally, and when one element fails. The apparatus incorporates a multi-stable stage and an output logic stage. The multi-stable stage detects state transitions in the input signals of each clock element and generates a corresponding clock-tracking signal which can disable the output of the corresponding clock from propagating through the output logic. The output logic stage logically combines each clock signal with its corresponding clock-tracking signal, and logically combines the resultant signal to produce a single stream of output signals responsive to a next transition produced by either of the two clock elements.

Abstract: A digital data processing apparatus utilizes a common bus structure for transferring information between functional units, including a processing unit, a peripheral control unit, and first and second memory units. Unit-to-unit information transfers are executed on the bus structure by pipelining signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. A signalling element periodically generates a first signal indicative the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle.

Abstract: A computer system of the type having a processor section, a memory section, an input-output section, a system clock, and a system bus for communicating signals between the sections, accommodates a variable number of processor units in the processor section. The processor section hence is expandable. Synchronization is distributed in that each processor unit can synchronize all the units in the processor section. The processor units arbitrate for access to the system bus, and respond to interrupts, on a distributed basis. A distribution counter in each processor unit provides a periodically sequencing unique count to distribute tasks among the processor units.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

Abstract: A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit.