Abstract: A method and a system for recovering a computing system's hardware state. In one embodiment the method includes simulating a removal of a hardware device from a bus of the computing system, simulating the replacement of the hardware device onto the bus and executing a configuration program for the computing system. In another embodiment the removal of the hardware device from the bus is simulated following a detection of a fault in the computing system. In another embodiment the simulating of the removal of the hardware device from the bus includes modifying a list of hardware devices connected to the bus by removing the hardware device from the list.

Abstract: The invention relates to checkpointing a disk and/or memory. In one aspect, a first computing device receives a write request that includes a data payload. The first computing device then transmits a copy of the received write request to a second computing device and writes the data payload to a disk. The copy of the write request is queued at a queue on the second computing device until the next checkpoint is initiated or a fault is detected at the first computing device. In another aspect, a processor directs a write request to a location within a first memory. The write request includes at least a data payload and an address identifying the location. An inspection module identifies the write request before it reaches the first memory, copies at least the address identifying the location, and forwards the write request to a memory agent within the first memory.

Abstract: The invention includes a method for determining whether a node in a non-recursive network can be removed. The method includes the steps of executing a reachability algorithm for a resource of a system upon initialization of the system. The resource is accessible to the system upon the initialization. A safe to pull manager evaluates the reachability algorithm for each node situated on the network to determine whether the node can be removed without interrupting resource accessibility to the system.

Abstract: The invention relates to computer systems, and more specifically to a method and apparatus for inserting and storing server units in a rack-mounted computer. In one embodiment, the system includes a cabinet comprising a plurality of rails. The system also includes a rack that is coupled to the rails for receiving the server units. A mounting latch is pivotally coupled to the server unit, the mounting latch including a fastener that is securable to the rails.

Abstract: A highly-available computer system is provided. The system includes at least two computer subsystems, each including memory, a local storage device and an embedded operating system. The system also includes a communication link between the two subsystems. Upon the initialization of the two computer subsystems, the embedded operating systems communicate via the communications link and designate one of the two subsystems as dominant. The dominant subsystem then loads a primary operating system. As write operations are sent to the local storage device of the dominant system, the write operations are mirrored over the communications link to each subservient system's local storage device. In the event of a failure of the dominant system, a subservient system will automatically become dominant and continue providing services to end-users.

Abstract: Systems and methods are disclosed for facilitating synchronous communications over an asynchronous communications link. Specifically, embodiments of the claimed invention provide systems and methods for transmitting high-speed signals while maintaining lock-step determinism using remote clock phase adjustments. Embodiments of the claimed invention also provide systems and methods for maintaining determinism through the use of synchronized time slice counters within the various components.

Abstract: The invention relates to checkpointing memory. In one aspect, a processor directs a write request to a location within a first memory. The write request includes at least a data payload and an address identifying the location. An inspection module identifies the write request before it reaches the first memory, copies at least the address identifying the location, and forwards the write request to a memory agent within the first memory.

Abstract: Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical instructions communicates transactions to at least one target device, such as input/output device, or another data processing element. The transactions are communicated through the asynchronous switching fabric wherein each of the data processing elements and the target device are connected to the asynchronous switching fabric through a respective channel adapter.

Abstract: In a computer system having a bus architecture, a system and process for isolating a device from a bus without interrupting system operation is described, the system including bus interface logic monitoring and reporting activity on the bus, isolation control logic receiving error signals from error detectors, and isolation switches through which devices are interconnected to the bus, the isolation switches allowing for the isolation of the devices from the bus. The isolation control logic determines the devices to be isolated responsive to the reported error and, in turn, transmits an isolation switch control signal to the isolation switch(es) associated with the identified device(s) to isolate those device(s) from the bus. In some embodiments, errors are reported by system software, input/output virtual address error detectors for systems using virtual memory addressing, protocol error detectors, and sensors sensing the physical removal of a bus-connected device from its bus interface slot.

Abstract: A method for generating a file object identifier. A computer allocates memory to store the identifier. The disk volume holding the file object, the disk block holding the file object, and the value of the offset within the disk block holding the file object are stored in the allocated memory. In one embodiment, the file object is a file, a directory, or a symbolic link. In another embodiment, the memory allocated is 32 bits. In yet another embodiment, the disk volume value is a 4-bit value. In still another embodiment, the disk block value is a 23-bit value. In another embodiment, the block offset value is a 5-bit value. In another embodiment, the offset within the disk block is a multiple of 128 byte increments. In one embodiment, the generated file object identifier is a PORTABLE OPERATING SYSTEM INTERFACE (POSIX) file serial number.

Abstract: An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass storage device. The fault-tolerant server also establishes communications between a second computing element and a second local mass storage device. In one embodiment, the first computing element and the second computing element issue substantially similar instruction streams to one of the local mass storage devices.

Abstract: The present invention relates to a method and system for transferring portions of a memory block. A first data mover is configured with a first start address corresponding to a first portion of a source memory block. A second data mover is configured with a second start address corresponding to a second portion of the source memory block sized differently from the first portion. The first portion of the source memory block is transferred by the first data mover and the second portion of the source memory block is transferred by the second data mover.

Abstract: An apparatus and method for a first computing element and a second computing element to execute in lockstep in a fault-tolerant server. In one embodiment, the first computing element provides a first instruction to a communications link and the second computing element provides a second instruction to a communications link. In one embodiment, a first local input-output (I/O) subsystem and a second local I/O subsystem are each in communication with the communications link. The first and/or the second local I/O subsystem compare the first instruction and the second instruction. In one embodiment, the first and second local I/O subsystems indicate a fault of the first computing element or the second computing element. Such a fault may be determined by a miscompare of the first instruction and the second instruction.

Abstract: A method and apparatus for storing transactional information in persistent memory. In one embodiment, the invention features a persistent volatile memory and an intermediary program in communication with the persistent volatile memory. The intermediary program receives transactional information and stores the information in the persistent volatile memory. A computer uses the intermediary program to enable the contents of the persistent volatile memory to remain unaltered during a failure of the computer. Additionally, the intermediary program may determine whether the transactional information meets a predetermined criteria before storing the information in the persistent volatile memory.

Abstract: A method and apparatus for input/output virtual address translation and validation assigns a range of memory to a device driver for its exclusive use. The device driver invokes system functionality for receiving a logical address and outputting a physical address having a length greater than the logical address. Another feature of the invention is a computer system providing input/output virtual address translation and validation for at least one peripheral device. In one embodiment, the computer system includes a scatter-gather table, an input/output virtual address cache memory associated with at least one peripheral device, and at least one device driver. In a further embodiment, the input/output virtual address cache memory includes an address validation cache and an address translation cache.

Abstract: Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.

Abstract: A method and apparatus for managing session information. In one embodiment, a communication session is established between a client computer and a server computer. When the client computer and the server computer establish the communication session, the client or the server typically stores information about the communication session, which is referred to as “session information.” The session information is stored in a first log file stored in a persistent volatile memory and in a cache file stored in a volatile memory of the server. The cache file is reconstructed after a server failure by retrieving the session information stored in the first log file.

Abstract: A method and apparatus for persistent volatile computer memory. In one embodiment, the memory of a computer in partitioned into two regions, one directly accessible to the operating system and one accessible to the operating system only through an intermediary program such as a device driver. In another embodiment, the partitioning of computer memory is achieved through modifications to the computer's BIOS, preventing the operating system from directly addressing a region of volatile computer memory and protecting the contents of the region from modification during a boot cycle.

Abstract: A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for bitwise comparing the CPU data output streams. The first CPU data output stream is transmitted to peripheral devices if both CPU outputs remain substantially identical. Otherwise, if the comparator indicates differences, queued first and second CPU data are routed to the first and second FIFOs respectively, and subsequent data are retained in respective CPU buffers. While the CPUs continue processing, ongoing diagnostic procedures attempt to identify one or the other of the CPUs as malfunctioning and the remaining CPU as correctly-functioning. If the resulting diagnosis is inconclusive, the CPU having the lower rate of error correction is identified as being correctly-functioning.

Abstract: Methods and apparatus for providing improved maintenance of consistent, redundant mass storage images. In one embodiment, one feature of the invention is the presence of non-volatile storage and persistent volatile memory, where the persistent volatile memory is used to store write transactions posted to non-volatile storage. Another feature of the invention is an intermediary program, such as a device driver, that serves as an intermediary between the operating system and non-volatile storage that processes write requests from the operating system directed to non-volatile storage, stores their contents in persistent volatile memory, and then completes the write to non-volatile storage. Yet another feature of the invention is that the contents of the persistent memory region are resistant to initialization or modification during a boot cycle.