Abstract: Disclosed is a novel structure and process for detecting protocol errors on a communications bus. According to one aspect of the invention, a protocol error detector comprises a physical error detector, a sequential error detector, and a logical error detector, each detecting physical, sequential, and logical protocol violations, respectively, and signaling a bus transaction error when a protocol violation is detected. In one embodiment, the protocol error detector substantially simultaneously checks each bus transaction for physical, sequential, and logical protocol violations. In another embodiment, the protocol error detector signals a detected bus transaction protocol violation substantially coincident with the bus transaction.

Abstract: Systems and methods for implementing improved disk caching in a programmed computer. Improved disk caching is achieved through apparatus and methods that permit the designation of files or types of files as memory-resident, transient, or normal (i.e., neither memory-resident or transient). The disk blocks associated with a memory-resident file are loaded immediately into cache memory in whole or in part, or are loaded on a block-by-block basis as they are accessed. The blocks of a memory-resident file remain in cache until the file is designated not memory resident, whereupon the blocks become purgeable, or until cache size limits force the removal of blocks from the cache. The blocks are purged immediately in whole or in part, or displaced gradually as blocks from other memory-resident files displace them. The blocks of a transient file are maintained in cache for a shorter duration before removal, freeing resources to cache other blocks.

Abstract: A computer system includes a port duplex driver (PDD) that creates a “virtual SCSI adaptor,” to control the operations of one or more redundant SCSI adaptors. During boot-up operations or when the status of a device on a SCSI bus changes, the PDD identifies the virtual SCSI adaptor as the only adaptor that provides access to particular storage devices on the SCSI bus. System components then direct data transfer operations through the virtual SCSI adaptor to the storage devices. The PDD intercepts commands that are directed through the virtual SCSI adaptor, and redirects the commands to a selected one of the actual SCSI adaptors. The selected SCSI adaptor then operates in a conventional manner, to translate the generic commands from the system components to device-specific commands for the storage devices on the SCSI bus. If the selected SCSI adaptor fails, the PDD redirects the data transfer operations instead through one of the redundant SCSI adaptors.

Abstract: A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a processor-reported an environmental condition is stored in a register and all processors are interrupted simultaneously. Upon interrupt, each processor reads the contents of the register and responds by adjusting its local clock rate synchronously with the other processors. In another embodiment, the processor's environmental status is polled by software control. Upon notification of an environmental condition, the software control notifies each processor to adjust its local clock rate synchronously with the other processors.

Abstract: The inventive system essentially hides redundant paths to the peripheral devices from the operating system, by reporting a single “virtual” path to the peripheral busses over PCI bus 0. The virtual path includes at least a virtual peripheral bus controller and a virtual video controller. The system also tells the operating system that the real controllers are on another PCI bus on an opposite side of a PCI-to-PCI bridge connected also to PCI bus 0. An I/O system manager selects one of the actual paths, which may, but need not, be connected to PCI bus 0, to handle communications with the peripheral devices. The I/O system manager maintains the controllers on the unselected path in an off-line or standby mode, in case of a failure of one or more of the controllers on the selected path. If a failure occurs, the I/O system manager performs a fail-over operation to change the selection of controllers, and the peripheral devices continue to operate in the same manner on the peripheral busses.

Abstract: A fault-tolerant maintenance bus protocol and method for using the same enables communication between a command module located on a parent maintenance bus and a plurality of subsystem components joined together on a child maintenance bus. The child maintenance bus is interconnected to a bridge assembly that directs messages formatted in the protocol between the subsystem components and the command module through the bridge. The protocol includes a command message structure that uniquely addresses the bridge assembly. It also includes a command string, a command data string for communicating with one of the subsystem components and a command error-checking string. A response message structure is generated by the bridge in response to a command message. The response message uniquely addresses the command module. It includes error and status strings with respect to execution of the command message, a response data string for communicating with the command module and a response error-checking string.

Abstract: A method for deterministically booting a computer system having redundant components includes the step of selecting hardware and software components. The selected components are booted in a manner consistent with traditional computer systems. If the boot fails, a different set of components is selected and an attempt is made to boot those components traditionally. In one embodiment, the hardware and software components are a processor and an input/output controller. A corresponding apparatus is also discussed.

Abstract: The inventive system includes an I/O subsystem that controls the synchronization of an off-line CPU to an on-line CPU, such that much of the synchronization operation takes place essentially as a background task for the on-line CPU. The I/O subsystem requests that the on-line CPU provide certain register and memory state information to general purpose registers on an I/O board. The I/O subsystem then provides the register contents to general purpose registers on the off-line CPU board, and the off-line CPU uses the information to set the states of certain of its registers and memory. The I/O system further includes a DMA engine that, at a time set by the I/O subsystem, copies pages of memory from the on-line CPU to the off-line CPU. At the end of the synchronization operation, the off-line CPU is directed to write to a predetermined register on the I/O board. When the off-line CPU performs the write operation, it indicates that the off-line CPU is in a known state and ready to go on-line.

Abstract: A fault-tolerant maintenance bus architecture provides dual maintenance buses interconnecting each of a plurality of parent circuit boards. The two maintenance buses are each connected to a pair of system management modules (SMMs) that are configured to perform a variety of maintenance bus activities. Within each parent board are a pair of redundant bridges each having a unique address. One bridge is connected to the first maintenance bus while a second bridge is connected to the second maintenance bus of the pair. A child maintenance bus interconnects the two bridges one a child circuit board. The child maintenance bus is itself interconnected with a variety of monitor and control to functions on maintenance bus-compatible subsystem components. The SMMs can address components on each child board individually and receive appropriate responses therefrom. In the event of a bus failure, the other bus can still communicate with child subsystem components via the unaffected bridge.

Abstract: A hot plug switch mechanism includes a card chassis and a motherboard in the chassis, the motherboard including a power bus, a plurality of connectors for connecting to a corresponding plurality of circuit boards and separate power switches connected between the power bus and each connector, each switch having an open position and a closed position. The switch mechanism also includes a plurality of actuator assemblies on the chassis corresponding to the plurality of switches on the motherboard each actuator assembly adapted to close the corresponding switch on the motherboard when the corresponding connector is connected to a circuit board. Preferably, each power switch is a Hall Effect switch and each actuator assembly includes a magnet which may be moved into proximity to the corresponding switch when the corresponding connector is connected to the circuit board.