Abstract: Provided is a process of measuring a space between a melt surface and a seed crystal provided above a melt, a process of lowering the seed crystal based on the space and bringing the seed crystal into contact with the melt, and a process of growing a single crystal by pulling the seed crystal while maintaining contact with the melt. Images of the seed crystal and the melt surface are captured by a camera installed diagonally above the melt surface, a real-image edge approximation circle is generated by approximating a circle from an edge pattern at a lower end of a straight-trunk portion of a real image of the seed crystal, and a mirror-image edge approximation circle is generated by approximating the circle from an edge pattern at the straight-trunk portion of a mirror image of the seed crystal reflected on the melt surface.

Abstract: A method of evaluating a silicon single-crystal ingot, the method including cutting out three or more plural silicon wafers from the ingot to be evaluated; mirror polishing the plural silicon wafers to yield silicon mirror-surface wafers; processing the plural silicon mirror polished wafers into silicon epitaxial wafers through formation of an epitaxial layer on the mirror polished surfaces; acquiring light point defect maps of the epitaxial layer surfaces of the plural silicon epitaxial wafers with a laser surface inspection device; and creating an overlay map. In a case where a light point defect group in which three or more light point defects are linearly distributed is not confirmed in the overlay map, a region, from which the plural silicon wafers have been cut out, in the silicon single-crystal ingot to be evaluated, is estimated not to be a region in which a twin has occurred.

Abstract: There is provided a growing method of monocrystalline silicon including: pulling up monocrystalline silicon from a dopant-added melt in which a dopant is added to a silicon melt and growing the monocrystalline silicon according to Czochralski process, in which the monocrystalline silicon is grown by calculating a critical CV value, which is a product of a dopant concentration C and a pull-up speed V at a point of time when an abnormal growth occurred in the monocrystalline silicon; and controlling at least one of the dopant concentration C or the pull-up speed V to make a CV value, which is a product of the dopant concentration C and the pull-up speed V at the point of time, below the critical CV value.

Abstract: A production method of a monocrystalline silicon includes adding red phosphorus in a silicon melt so that an electrical resistivity of the monocrystalline silicon falls in a range of 0.5 m?·cm or more and less than 0.7 m?·cm; and pulling up the monocrystalline silicon so that a time for a temperature of at least a part of a straight body of the monocrystalline silicon to be within a range of 570° C.±70° C. is in a range from 10 minutes to 50 minutes.

Abstract: A processing condition setting apparatus includes a controller that selects a parameter set to be applied to the wafer processing apparatus from a plurality of parameter sets. The controller estimates, for each of the parameter sets, the post-processing characteristics of the wafer to be processed, based on the pre-processing characteristics of the wafer to be processed and the processing data, assuming that the wafer to be processed has been processed by applying each of the parameter sets. The controller calculates two or more indicators for each of the post-processing characteristics and obtains constraints on the indicators. The controller selects a parameter set, which is to be applied to the wafer processing apparatus when processing the wafer to be processed, from among the conformed parameter sets in which the indicators satisfy the constraints.

Abstract: An epitaxial wafer includes a silicon substrate having an epitaxial layer of 0.3 ?m to 1.0 ?m thickness and thickness variation of 1% or less, the thickness variation being a percent difference between thicknesses at any two symmetrical points of the epitaxial layer about 10 mm inward from an outer edge of the epitaxial wafer. A preparation method includes placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotation rate (D); and applying a source gas to grow an epitaxial layer of a desired thickness (B) at a growth rate (A). The source gas is applied for a growth time (C) that satisfies C=B/A and the rotation rate (D) is selected from a range of 22 to 70 rpm that allows the susceptor to rotate to an exact integer number of turns (E) based on a relationship D=E/C.

Abstract: An epitaxial wafer includes a silicon substrate having a top surface and an epitaxial layer on said top surface, wherein the epitaxial layer has a thickness in a range of 0.3 ?m to 1.0 ?m, and a thickness variation of 1% or less. A method of preparing such epitaxial wafer includes placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotation rate (D); and applying a source gas in the epitaxial reactor to grow an epitaxial layer of a desired thickness (B) at a growth rate (A) on the silicon substrate; wherein the source gas is applied for a growth time (C) that satisfies C=B/A and the rotation rate (D) is selected from a range of 22 to 70 rpm that allows the susceptor to rotate to an exact integer number of turns (E) based on a relationship D=E/C.

Abstract: This disclosure aims to provide a double-side polishing apparatus for a workpiece and a double-side polishing method for a workpiece, capable of suppressing roll-off of the outer peripheral shape of the workpiece. The temperature of polishing slurry is individually adjusted for each of a plurality of slurry supply systems.

Abstract: A method of creating a correlation relational formula for determining a polishing condition, the method including polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane polishing amount distribution information on the semiconductor wafers in polishing under the plurality of polishing conditions; polishing semiconductor wafers under a plurality of polishing conditions including a plurality of polishing parameters, and acquiring, by actual measurement, in-plane temperature distribution information during semiconductor wafer polishing in polishing under the plurality of polishing conditions, or creating in-plane temperature distribution information during semiconductor wafer polishing under polishing conditions including a plurality of polishing parameters by heat transfer analysis, and correlating relational formulas between a semiconductor wafer in-plane temperature distribution parameter and a plura

Abstract: A quartz glass crucible that allows an increase in strength during crystal pulling up, by forming a thick crystal layer on an outer surface of the crucible at an appropriate crystallization rate is provided. A quartz glass crucible includes a crucible base body made of silica glass and a crystallization accelerator-containing coating film formed on the outer surface of the crucible base body. 10 hours after a start of a heat treatment performed in an Ar atmosphere at a furnace temperature of 1580° C. and a furnace pressure of 20 Torr, a thickness of an outer surface crystal layer formed on the outer surface of the crucible base body is 0.21 to 0.5 mm and a crystallization rate is 21 to 50 ?m/hr. A crystallization rate of the outer surface after 20 hours from the start of the heat treatment is 10 ?m/hr or less.

Abstract: A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.

Abstract: A semiconductor manufacturing including plurality of processors and a number of loader-unloaders exceeding thereof. Each object to be treated is transported to a processor in a single unit and treated, and then is transported to the loader-unloader. The manufacturing lot of the object to be treated by each processor is carried into each loader-unloader while the remaining loader-unloader is left empty, thereafter each of the processors starts treatment, and while the object to be treated is being treated by each processor, based on manufacturing information of the object to be treated for each processor, the processor that finishes treatment relatively early is predicted, and before finishing the treatment by each processor, the manufacturing lot to be treated by the processor that has been predicted to finish treatment relatively early is carried into the loader-unloader that is currently empty.

Abstract: A heating portion heats a silicon melt in a quartz crucible. The heating portion includes: a heat generation portion integrally molded into a cylinder; and four power supply portions for supplying electric power to the heat generation portion. When the heating portion is divided by a virtual plane into two including a first heating region located on one side of the heat generation portion and a second heating region located on the other side of the heat generation portion with respect to the virtual plane, the virtual plane passing through a center axis of the heat generation portion and being perpendicular to the heat generation portion and parallel to a central magnetic field line of a horizontal magnetic field applied to the silicon melt, a heat generation amount of the first heating region and a heat generation amount of the second heating region are set to different values.

Abstract: A vapor deposition device is provided that can suppress an influence on an epitaxial layer which is caused by a position of a lift pin without adjusting an upper and lower heating ratio of a wafer. A reaction chamber is provided with a susceptor on which a carrier is placed, and a carrier lift pin which moves the carrier vertically relative to the susceptor; and the carrier lift pin is installed outside of an outer edge of the wafer when a state where the carrier supporting the wafer is mounted on the susceptor is viewed in a plan view.

Abstract: In order to have uniform dot holes even when a deep laser mark of approximately 100 ?m depth is formed, a silicon wafer having a crystal plane orientation of (100) has an identification mark configured by a plurality of dot holes on a surface with a surface roughness of 0.15 to 0.60 nm. A ratio between a length in a <100> direction and a length in a <110> direction of an opening of the dot hole on a wafer surface is 1 to 1.10, the length in the <100> direction of the opening is 80 ?m to 110 ?m, a depth of the dot hole in a cross-section is 80 ?m to 110 ?m, and a bottom surface of the dot hole is a flat surface of a (100) plane.

Abstract: A wafer polishing method includes acquiring in-plane thickness distribution information regarding a wafer to be polished or a wafer subjected to the same processing treatment, determining a difference in pressure between a pressure Pc to be applied to the central part of the wafer by introducing a gas into the central region and a pressure Pe to be applied to the outer peripheral part of the wafer by introducing a gas into the outer peripheral region, determining any one pressure of Pc and Pe, and determining the other pressure, determining the pressure Pg to be applied, based on a set value Pr of a contact pressure to be applied to the lower surface of the second ring-shaped member due to contact with the polishing pad at the time of polishing, and bringing the lower surface of the wafer into contact with the polishing pad to conduct polishing.

Abstract: A method for controlling a pulling apparatus for a single crystal silicon ingot includes: obtaining actual results data that relates a measured value of oxygen concentration of a single crystal silicon ingot produced by the pulling apparatus and an operation amount of the pulling apparatus during production, generating an estimation model that estimates the oxygen concentration of a single crystal silicon ingot to be produced by the pulling apparatus based on the actual results data, adjusting the operation amount to be input to the estimation model so that an estimated value of the oxygen concentration of the single crystal silicon ingot by the estimation model becomes target concentration, and determining the adjusted operation amount as the operation amount for producing a single crystal silicon ingot in the next batch of the pulling apparatus.

Abstract: There is provided a cushioning material, the cushioning material including a lower cushioning material that supports a lower portion of each of two rows of containers on a lower tier, middle cushioning materials that are interposed between the containers on an upper tier and the containers on the lower tier, and upper cushioning materials that are disposed in each of the two rows of the containers on the upper tier and that hold each of an upper portion of the containers on the upper tier, in which the lower cushioning material is formed without a space between the lower cushioning material and side plates of a packing case and the middle cushioning materials and the upper cushioning materials are formed with a predetermined space between the middle cushioning materials and the upper cushioning materials and the side plates of the packing case.

Abstract: Provided is a method capable of efficiently polishing the front and back sides of a carrier plate unused after manufacture, which is used in a double-sided polishing process for semiconductor wafers. The method comprises: sandwiching a carrier plate unused after manufacture and to be polished between an upper surface plate and a lower surface plate in the double-sided polishing apparatus, and supplying a polishing liquid while relatively rotating the carrier plate to be polished, the upper surface plate, and the lower surface plate to polish both sides of the carrier plate to be polished, wherein a polishing pad including, on its surface, an abrasive grain-containing layer in which abrasive grains of 2 ?m or more in grain size are embedded is used as a polishing pad in a double-sided polishing apparatus.

Abstract: A method for modeling a wafer profile by a function is provided in which the function is used for calculating a displacement z in a thickness direction of a wafer and is a sum of plural functions. The first function g(r) has a distance r from the center of the wafer as a variable. The second function Ar×h(N?) indicates multiplying a sine or cosine function h(N?), with a first angle ? with reference to a predetermined position in a circumferential direction of the wafer as a variable and an integer N as a constant, by a coefficient A with the distance r. The third function Br×i(M(?-?)) indicates multiplying a sine or cosine function i(M(?-?)), with the first angle ? as a variable, a second angle ? with reference to the predetermined position as a constant, and an integer M as a constant, by a coefficient B and the distance r.