Patents Assigned to Sumitomo Electric Device Innovations, Inc.
  • Publication number: 20250054841
    Abstract: A package includes a base having a mounting region on which a semiconductor chip is to be mounted, a frame provided on the base so as to surround the mounting region, a first metal layer provided on an upper surface of the frame, the first metal layer including a first portion to which a first bonding wire electrically connecting the semiconductor chip is to be bonded, a second portion farther from the mounting region than the first portion, and a first connecting portion connecting the first portion to the second portion, a first insulating layer provided on the first connecting portion in contact with the first connecting portion, the first insulating layer crossing the first metal layer, and a first lead bonded on the second portion.
    Type: Application
    Filed: May 3, 2024
    Publication date: February 13, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Ikuo NAKASHIMA
  • Patent number: 12222562
    Abstract: An optical apparatus includes a light emitting apparatus and a host apparatus. The light emitting apparatus includes a housing extending in a first direction, a light emitting device mounted in the housing, an optical connector including a first optical connection part provided at one end of the housing, and an electrical connector including a first electrical connection part provided at one end of the housing and receiving a voltage to drive the light emitting device. The host apparatus includes a host optical connector including a second optical connection part which faces the first optical connection part and is optically coupled thereto, a host electrical connector including a second electrical connection part facing the first electrical connection part and being electrically connected to the first electrical connection part, and a host board mounting the host optical connector and the host electrical connector thereon.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 11, 2025
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Kuniyuki Ishii, Hiromi Kurashima, Hideaki Kamisugi, Tomomi Sano, Tetsuya Nakanishi, Hong Chuyen Nguyen, Hajime Arao, Dai Sasaki, Takuro Watanabe
  • Publication number: 20250047057
    Abstract: An optical modulator integrated laser includes a substrate, a laser portion provided on the substrate and outputting laser light, an optical modulation portion provided on the substrate and modulating the laser light, and a first terminating portion provided on the substrate and including a first resistive film. The optical modulation portion includes a modulation electrode that is supplied with a modulation signal, a signal pad connected to the modulation electrode and for being connected to a first wire for inputting the modulation signal to the optical modulation portion, and a first pad for being connected to a second wire having a ground potential. The modulation electrode and one end of the first resistive film are connected to each other. Another end of the first resistive film and the first pad are connected to each other.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 6, 2025
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiromitsu KAWAMURA
  • Publication number: 20250047056
    Abstract: An optical modulator integrated laser includes a substrate, a laser portion provided on the substrate and outputting laser light, an optical modulation portion provided on the substrate and modulating the laser light, and a first terminating portion provided on the substrate and including a first resistive film. The optical modulation portion includes a modulation electrode that is supplied with a modulation signal, a signal pad connected to the modulation electrode and for being connected to a first wire for inputting the modulation signal to the optical modulation portion, and a first pad for being connected to a second wire having a ground potential. The signal pad and one end of the first resistive film are connected to each other. The other end of the first resistive film and the first pad are connected to each other.
    Type: Application
    Filed: July 29, 2024
    Publication date: February 6, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Hiromitsu KAWAMURA
  • Patent number: 12198978
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor layer on an upper surface of a substrate, forming an etching stopper on an upper surface of the semiconductor layer, forming a metal mask including a seed film and a plating film on a lower surface of the substrate, the metal mas having an opening inside the etching stopper in plan view, forming a through-hole in the substrate and the semiconductor layer from the lower surface of the substrate to the etching stopper through the opening, and removing the plating film by an anodic reaction in an electrolyte solution after forming the through-hole.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: January 14, 2025
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shouhei Kitajima, Ryo Kasai
  • Publication number: 20250015123
    Abstract: An electronic component includes an insulator, a first resistor provided on the insulator, a first electrically insulating film provided on the first resistor to be in contact with the first resistor, and a first metal bonding material provided on the first electrically insulating film to be in contact with the first electrically insulating film and be in contact with a heat sink.
    Type: Application
    Filed: June 12, 2024
    Publication date: January 9, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Ikuo NAKASHIMA
  • Patent number: 12188149
    Abstract: A method of manufacturing a semiconductor device, includes attaching a first susceptor to a film forming apparatus, measuring a magnitude of a warp of the first susceptor, setting a first initial film formation condition as a film formation condition of the film forming apparatus in accordance with the measured magnitude of the warp of the first susceptor, and placing a plurality of first wafers on the first susceptor and forming a first film on the plurality of first wafers under the film formation condition. The setting of the first initial film formation condition includes reading the first initial film formation condition from a recording medium storing a database. The database includes a plurality of pieces of data in which magnitudes of warps of susceptors are associated with initial film formation conditions for forming the first film.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: January 7, 2025
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Kohei Miyashita
  • Publication number: 20250006688
    Abstract: A semiconductor device includes a cavity package including a substrate and at least one output lead disposed higher than the substrate, in a side view, to create a cavity. A transistor die is disposed within the cavity. A top surface of the transistor die is lower than a top surface of the output lead when viewed in the side view. A first substrate is disposed within the cavity and is separate from the transistor die. A top surface of the first substrate is lower than the top surface of the output lead in the side view. A shunt wire connects an output of the transistor die to the first substrate, and an output wire connects the output of the transistor substrate to the output lead. The shunt wire or the output wire is disposed and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Seiya TAKASHIMA
  • Publication number: 20250006595
    Abstract: A semiconductor device includes a substrate, a first unit FET including first source, first drain, and first gate electrodes, a second unit FET including second source, second drain, and second gate electrodes, a first source wiring electrically contacting the first source electrode, a gate bus bar electrically connected to the first gate electrode, and interposing the first gate electrode between the gate bus bar and the second gate electrode, and a gate wiring provided above the first source electrode in non-contact with the first source electrode, and electrically connecting the gate bus bar and the second gate electrode, wherein a maximum width in a first direction of a region where the first source wiring contacts the first source electrode is ½ times or more a maximum width in the first direction of a region where the first source wiring overlaps the first source electrode.
    Type: Application
    Filed: June 18, 2024
    Publication date: January 2, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Yuya TSUTSUMI
  • Publication number: 20250006624
    Abstract: A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode, and a second drain electrode, a gate wiring provided between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer electrically connected to the first source electrode, at least an upper portion of the first cover metal layer projecting toward the gate wiring more than the first source electrode, and a second cover metal layer electrically connected to the second source electrode, at least an upper portion of the second cover metal layer projecting toward the gate wiring more than the second source electrode.
    Type: Application
    Filed: June 11, 2024
    Publication date: January 2, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Hiroaki MARUYAMA
  • Publication number: 20250006809
    Abstract: A semiconductor device includes a substrate, a first transistor unit having a first drain electrode, a first gate electrode, and a first source electrode, a second transistor unit having a second source electrode, a second gate electrode electrically, and a second drain electrode, a gate wiring provided on the substrate between the first source electrode and the second source electrode and electrically connected to the first gate electrode and the second gate electrode, a first cover metal layer provided above the substrate between the first source electrode and the gate wiring and adjacent to the first source electrode and the gate wiring, and electrically connected to the first source electrode, and a second cover metal layer provided above the substrate between the second source electrode and the gate wiring and adjacent to the second source electrode and the gate wiring, and electrically connected to the second source electrode.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Hiroaki MARUYAMA
  • Patent number: 12154871
    Abstract: A microwave circuit integrated on a common semiconductor substrate, includes: a first-stage amplifier to amplify an input high-frequency signal having a first frequency; a main-system amplification stage to amplify and output one signal having the first frequency branched from an output of the first-stage amplifier; a branch stage to generate a signal having double the frequency of the first frequency; and a sub-system amplification stage to amplify and output the signal having double the frequency. An amplification circuit constituting the first-stage amplifier, an amplification circuit included in the branch stage, an amplification circuit included in the main-system amplification stage, and an amplification circuit included in the sub-system amplification stage are connected in series between a power supply and ground in a DC manner, and each is a current reuse type amplifier including two-stage transistors connected in series between a signal input and a signal output in an AC manner.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 26, 2024
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Kenshi Naito
  • Publication number: 20240388255
    Abstract: A radio frequency amplifier circuit includes a Doherty amplifier including a main amplifier and a peak amplifier. The main amplifier includes a first input end, a first output end, and a first transistor. The main amplifier includes only a first harmonic processing circuit among the first harmonic processing circuit and a first fundamental matching circuit. The peak amplifier includes a second input end, a second output end, and a second transistor. The peak amplifier includes only a second fundamental matching circuit among a second harmonic processing circuit and the second fundamental matching circuit.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 21, 2024
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Takuma MORI
  • Patent number: 12140806
    Abstract: An optical module includes a first optical splitting element to split a signal beam into a first polarization component and a second polarization component, a first element having a first introduction port, a second element having a second introduction port, a first condensing part disposed between the first optical splitting element and the first introduction port and configured to condense the first polarization component toward the first introduction port, and a second condensing part disposed between the first optical splitting element and the second introduction port and configured to condense the second polarization component toward the second introduction port. An average refractive index of the second condensing part in an optical axis direction is larger than an average refractive index of the first condensing part in an optical axis direction.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 12, 2024
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Satoru Kanemaru
  • Publication number: 20240372325
    Abstract: A variable-wavelength laser includes a gain region and a wavelength control region alternately arranged along a propagation direction of light, a diffraction grating arranged in each of the gain region and the wavelength control region, and a region located at least one of an end of the gain region and an end of the wavelength control region at a boundary between the gain region and the wavelength control region, the region being without the diffraction grating, wherein a length of the region without the diffraction grating is 5% or more and 30% or less of a length of the gain region or the wavelength control region to which the region belongs.
    Type: Application
    Filed: March 31, 2022
    Publication date: November 7, 2024
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Noriaki KAIDA
  • Publication number: 20240372317
    Abstract: An optical modulator integrated semiconductor laser includes a laser unit outputting a laser beam, an optical modulation unit modulating the laser beam, a signal pad for connection to a first wire for inputting a modulation signal to the optical modulation unit, and a first pad for connection to a second wire holding a ground potential.
    Type: Application
    Filed: April 29, 2024
    Publication date: November 7, 2024
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiromitsu KAWAMURA
  • Patent number: 12125774
    Abstract: A semiconductor device includes a semiconductor chip in which a field effect transistor mainly containing GaN is formed on a surface of a SiC semiconductor substrate. The semiconductor device includes a metal base on which a back surface of the semiconductor chip is mounted through a conductive adhesive material containing Ag and a resin mold configured to seal the semiconductor chip. A metal having wettability lower than wettability of Au or Cu with respect to Ag is exposed in a region extending along an edge of the back surface.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: October 22, 2024
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Hisashi Shimura, Yoshiyasu Kuwabara
  • Patent number: 12126384
    Abstract: An optical transmitter includes: a controller that generates a multi-level amplitude modulated signal based on transmission data that is binary data; a driver that generates a drive signal in accordance with the multi-level amplitude modulated signal; and a light emitter that generates an optical signal in accordance with the drive signal. The controller selects one of a first encoding method and a second encoding method in accordance with a switching signal. The controller generates the multi-level amplitude modulated signal by converting a bit string of M (M is an integer of 2 or more) bits included in the transmission data into a pulse signal having 2M logic levels using a selected encoding method. The controller sets voltage values of the 2M logic levels depending on the selected encoding method.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: October 22, 2024
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Shinta Kasai
  • Patent number: 12119311
    Abstract: Provided is an amplifier device including a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The package includes a metal base, an insulating side wall, an input lead, and an output lead. The input lead is connected to a gate pad group of the semiconductor chip. The output lead is connected to a drain pad group of the semiconductor chip. Each of the feedback circuits includes a dielectric substrate disposed on the metal base, a feedback resistor located on the dielectric substrate, and a capacitor connected in series to the feedback resistor. Each of the feedback circuits is connected between the gate pad group and the drain pad group. The feedback circuits are located respectively on the base on one side and the other side of the semiconductor chip in an extension direction of a first and a second end edge.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: October 15, 2024
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Naoyuki Miyazawa
  • Publication number: 20240339967
    Abstract: A semiconductor amplifier circuit includes: a circuit board; a pre-stage amplifier including first and second transistors arranged side by side on the circuit board with a first reference line interposed therebetween; a post-stage amplifier disposed on the circuit board; and an inter-stage circuit formed on the circuit board, in which the inter-stage circuit includes: a phase adjustment line; an internal terminal; and a matching circuit, a first end of the phase adjustment line is connected to the output terminal, and a second end of the phase adjustment line is connected to the internal terminal, an input terminal of the matching circuit is connected to the internal terminal, and an output terminal of the matching circuit is connected to an input terminal of the post-stage amplifier, the first end and the second end are arranged on the first reference line, and the phase adjustment line has a line-symmetric shape.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 10, 2024
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Akio OYA