Patents Assigned to Sumitomo Electric Device Innovations, Inc.
  • Publication number: 20230094768
    Abstract: A semiconductor device includes a substrate, a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer and having a first opening formed therein, a gate electrode disposed on the insulating layer and in contact with the semiconductor layer via the first opening, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer. The gate electrode includes a crystallinity control film disposed on the insulating layer and having a second opening formed such that an inner wall thereof extends to an inner wall of the first opening toward the substrate in plan view in a direction perpendicular to a top surface of the substrate, and a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer via the inner walls, extending to each other, of the second opening and the first opening.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 30, 2023
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Yukinori NOSE
  • Patent number: 11604370
    Abstract: An optical modulator carrier assembly includes a optical modulator, a transmission line substrate, a first via, a second via and a wire having an inductor component provided on a second surface of the transmission line substrate, and electrically connecting between the another end of the first via and the another end of the second via. The one end of the first via, the cathode electrode pad, the terminating resistor, the one end of the second via are arranged on the in this order.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 14, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Masahiro Hirayama
  • Publication number: 20230076573
    Abstract: Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Ikuo NAKASHIMA, Shingo INOUE
  • Patent number: 11594507
    Abstract: A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 28, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Keita Matsuda
  • Patent number: 11589455
    Abstract: The electronic module including a metal base, a ceramic substrate, and a die-capacitor is disclosed. The ceramic substrate is mounted on the metal base via eutectic solder. The ceramic substrate includes a main substrate having a back surface facing the metal base and a front surface opposite to the back surface, and a back metal layer placed on the back surface of the main substrate and joined to the eutectic solder. The die-capacitor is mounted on the front surface of the ceramic substrate along one edge of the ceramic substrate. The back surface of the ceramic substrate is provided with an exposure region where the back metal layer is not provided. The exposure region includes a main region corresponding to an outer shape of the die-capacitor spreading along the front surface and an edge region extending from the main region to the one edge of the ceramic substrate.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 21, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Akitada Kodama, Masato Furukawa
  • Patent number: 11588441
    Abstract: A semiconductor amplifier 1 includes transistors 21a and 21b mounted side by side on a bottom plate 2 in a space in a package 6, a matching circuit 22a mounted between the transistors 21a, 21b on the bottom plate 2, a matching circuit 22b mounted on an opposite side of the transistor 21b from the transistor 21a on the bottom plate 2, an input terminal TIN installed on one side of a wiring substrate 3, an output terminal TOUT installed on the other side of the wiring substrate 3, and gate bias terminals T1G and T2G and drain bias terminals T1D and T2D installed at positions with the input terminal TIN and the output terminal TOUT of the wiring substrate 3, and the transistor 21a, the matching circuit 22a, the transistor 21b, and the matching circuit 22b are linearly placed between the input terminal TIN and the output terminal TOUT.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 21, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Naoyuki Miyazawa
  • Publication number: 20230051546
    Abstract: A semiconductor device includes a substrate having an upper surface and a lower surface, a metal layer provided on the lower surface of the substrate, a semiconductor element including first electrodes provided on the upper surface of the substrate, connected to the metal layer via through holes penetrating the substrate, and electrically separated from each other on the upper surface of the substrate, second electrodes provided on the upper surface of the substrate and alternately provided with the first electrodes, and a first pad provided on the upper surface of the substrate and to which the second electrodes are connected, and a protective film provided on the upper surface of the substrate to cover the first electrodes and the second electrodes, having a first opening that exposes at least a part of the first pad, and having no opening that overlaps the first electrodes.
    Type: Application
    Filed: July 14, 2022
    Publication date: February 16, 2023
    Applicant: Sumitomo Electric Device Innovations, Inc.
    Inventor: Takeshi HISHIDA
  • Patent number: 11581246
    Abstract: A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: February 14, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Shingo Inoue, Kaname Ebihara
  • Patent number: 11569788
    Abstract: An amplifier device includes a substrate, a composite packaged amplifier having a bottom plate and an output plate, a first amplifier and a second amplifier provided on the bottom plate, a combining node that combines an output of the first amplifier with an output of the second amplifier, an output matching circuits provided on the bottom plate, that has a first transmission line provided between the first amplifier and the combining node, and a second transmission line provided between the combining node and the second amplifier, a third transmission line having one transmission line on which the output plate is mounted and other transmission line that connects the one transmission line to the external port, and wirings connecting to one terminal of the output plate and the combining node. A length of the output plate and the other transmission line is equal or less than ?/4 radian for a signal.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: January 31, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: James Wong
  • Patent number: 11561186
    Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 24, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiroyuki Oguri
  • Patent number: 11557553
    Abstract: Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 17, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Ikuo Nakashima, Shingo Inoue
  • Patent number: 11557668
    Abstract: A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 17, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Ken Nakata
  • Patent number: 11552206
    Abstract: An optical waveguide type photodetector includes a first semiconductor layer of a first conductive type, a multiplication layer of a first conductive type on the first semiconductor layer, an optical waveguide structure, and a photodiode structure. The photodiode structure has a third semiconductor layer of a second conductive type, an optical absorption layer of an intrinsic conductive type or of a second conductive type, and a second semiconductor layer of a second conductive type. The optical waveguide structure includes an optical waveguiding core layer and a cladding layer. An end face of the photodiode structure located in a second region of the first semiconductor layer and an end face of the optical waveguide structure located in a first region of the first semiconductor layer are in contact.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: January 10, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihiro Yoneda, Takuya Okimoto
  • Publication number: 20230005736
    Abstract: A method for manufacturing an epitaxial substrate includes the steps of: epitaxially growing a group III nitride semiconductor layer on a substrate; removing the substrate from a growth furnace; irradiating a surface of the group III nitride semiconductor layer with ultraviolet light while exposing the surface to an atmosphere containing oxygen; and measuring a sheet resistance value of the group III nitride semiconductor layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: January 5, 2023
    Applicants: Sumitomo Electric Device Innovations, Inc., Sumitomo Electric Industries, Ltd.
    Inventors: Kohei MIYASHITA, Takeshi KISHI, Takumi YONEMURA
  • Publication number: 20220416901
    Abstract: An optical transmitter according to one embodiment includes a housing with an emission end, a light emitting element mounted on a first mounting portion of the housing, and a light receiving element mounted on a second mounting portion of the housing to monitor output light from the light emitting element. The second mounting portion is provided with a carrier, a first resin located on an emission end side of a lower side of the carrier, and a second resin located on a light emitting element side of the lower side of the carrier. A coefficient of thermal expansion of the first resin is smaller than a coefficient of thermal expansion of the second resin.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 29, 2022
    Applicants: Sumitomo Electric Industries, Ltd., Sumitomo Electric Device Innovations, Inc.
    Inventors: Satoshi YOSHIMURA, Hiroshi HARA, Eiji TSUMURA, Masanobu KAWAMURA
  • Publication number: 20220415833
    Abstract: A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are provided on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are provided between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Masahiro HIRAYAMA
  • Patent number: 11533026
    Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Naoyuki Miyazawa
  • Patent number: 11515208
    Abstract: A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 29, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Toshiyuki Kosaka, Shunsuke Kurachi
  • Patent number: 11508672
    Abstract: A semiconductor device including a base, a buffer member, a frame, a lid, and a semiconductor element, is disclosed. The ceramic frame is mounted on the copper base with the molybdenum buffer member interposed therebetween. The semiconductor element is sealed in a space within the frame defined by the lid. The frame includes a top portion, a lower stage portion that is disposed below the top portion and is provided with an input electrode and an output electrode, and an upper stage portion. The upper stage portion is formed in an arrangement direction of the input electrode and the output electrode, and is formed below the top portion and above the lower stage portion. The upper stage portion includes an upper stage connection portion formed on the periphery of the lower stage portion in a direction intersecting the arrangement direction of the input electrode and the output electrode.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 22, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tuneyuki Tanaka
  • Patent number: 11502011
    Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 15, 2022
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Tomoki Ohno