Abstract: Methods and systems for load balancing a plurality of entities, such as firewalls, in a network environment are disclosed. In particular, the load balancing of firewalls on a bidirectional traffic path is performed using a single device that controls both incoming and outgoing traffic through the firewalls. The single device may include virtual routers for controlling the bidirectional traffic through the firewalls. A first virtual router may control incoming traffic to the firewalls and the other virtual router may control outgoing traffic to the firewalls. The virtual routers are logical partitions of the device layered on the physical resources of the device. The virtual routers share all or portions of the physical resources of the single device.

Abstract: A method for processing packets that includes receiving a first packet for a first target on a host, prior to sending the packet to a Network Layer in the host, determining the first target of the first packet, obtaining a first target ID associated with the first target, obtaining a first virtual network stack (VNS) instance ID using the first target ID, and obtaining a first VNS Instance parameter using the first VNS instance ID, sending the first packet to the Network Layer, and processing the first packet in the Network Layer using the first VNS Instance parameter to obtain a first network processed packet.

Abstract: One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. The system then uses the clock signal to limit the maximum repetition rate of the asynchronous circuit so that only a predetermined number of asynchronous transactions may take place during each cycle of the clock signal.

Abstract: A system, method and apparatus for executing instructions in parallel identify a set of traces within a segment of code, such as Java bytecode. Each trace represents a sequence of instructions within the segment of code that are execution structure dependent, such as stack dependent. The system, method and apparatus identify a dependency order between traces in the identified set of traces. The dependency order indicates traces that are dependent upon operation of other traces in the segment of code. The system, method and apparatus can then execute traces within the set of traces in parallel and in an execution order that is based on the identified dependency order, such that at least two traces are executed in parallel and such that if the dependency order indicates that a second trace is dependent upon a first trace, the first trace is executed prior to the second trace.

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a BIST engine and a register. The BIST engine is capable of executing a built-in self-test and storing the results thereof, wherein the results include an indication of whether an executed built-in self-test is completed. The register is capable of storing the results of the executed built-in self-test, including the indication. A method for performing a built-in self-test comprises performing a BIST, including generating a indication of whether the built-in self-test is completed, and storing the indication.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: Mechanisms and techniques operate in a computerized device to perform a memory management technique such as garbage collection. The mechanisms and techniques operate to detect, within a storage structure associated with a thread, general memory references that reference storage locations in a general memory area such as a heap. The storage structure may be a stack utilized by the thread, which may be, for example, a Java thread, during operation of the thread in the computerized device. The system maintains a reference structure containing an association to the general memory area for each detected general memory reference within the storage structure. The system then operates a memory management technique on the general memory area for locations in the general memory area other than those for which an association to the general memory area is maintained in the reference structure, thus increasing the performance of the memory management technique.

Abstract: Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as load instructions on one or more processors in the computerized device. The mechanisms and techniques can execute a set of instructions on a processor in the computerized device and can detect a value of a speculation indicator. If the value of the speculation indicator indicates that speculative execution of load instructions is allowed in the computerized device, the mechanisms and techniques allow speculative execution of load instructions in the processor, whereas if the value of the speculation indicator indicates that speculative execution of load instructions is not allowed in the computerized device, the mechanisms and techniques do not allow speculative execution of load instructions in the processor.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 150 degree bump placement structures is provided.

Abstract: A novel N×N Crossbar Packet Switch is disclosed, which crossbar switch is based on a distributed port architecture, asynchronous output port arbitration, support of non fixed-size packets (cells), support for virtual channels (VC) and/or priority, and which only requires 2*N*N control lines for the arbitration.

Abstract: A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system.

Abstract: “A system [comprises] includes a virtual private network and an external device interconnected by a digital network. The virtual private network has a firewall, at least one internal device and a nameserver each having a network address. The internal device also has a secondary address, and the nameserver is configured to provide an association between the secondary address and the network address. The firewall, in response to a request from the external device to establish a connection therebetween, provides the external device with the network address of the nameserver. The external device, in response to a request from an operator or the like, including the internal device's secondary address, requesting access to the internal device, generates a network address request message for transmission over the connection to the firewall requesting resolution of the network address associated with the secondary address.

Abstract: A method of detecting congestion in a computer network uses a receiving station which determines a first number of messages missing in a first acknowledgment window. The station then determines a second number of messages missing in a subsequent acknowledgement window. The station then measures congestion on the network in response to an increase in the number of missing messages as indicated by the first number of missing messages in the first acknowledgement window and the second number of missing messages in the second acknowledgement window.

Abstract: A method providing an application computer program to be written independently of the structure of a directory information tree. The application program makes calls to an innovative API, the API accessing the structure of the directory information tree in an innovative template. If the structure of the directory information tree is changed, the template is changed, but the application is not changed.

Abstract: A multicast repair tree is established, the repair tree having one sender station and a plurality of repair head stations. A repair head station has an affiliated group of member stations. A repair head station retransmits a lost message to its affiliated group of member stations upon receipt from a member station of a NACK message indicating that the selected message was not received. Acknowledgment windows (ACK windows) are established in a member station for transmission of ACK or NACK message by the member station. A number of messages transmitted by the sender station during a transmission window is established. Also a same size of ACK window is established in the receiving stations, with a slot in the ACK window corresponding to each message transmitted by the repair head station. Each receiving station is assigned a slot in the ACK window during which time that receiving station transmits its ACK or NACK messages.

Abstract: A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.

Abstract: A PC board ejector assembly is provided for disengaging a first PC board from a second PC board in a computer chassis. The PC boards each includes at least one connector for connecting the first PC board to the second PC board. The chassis includes a divider wall. The PC board ejector assembly includes a mounting bracket positioned on at least one of the first and the second PC boards, and a disengagement member coupled to the mounting bracket. The mounting bracket is positioned on the PC board such that movement of the disengagement member engages the member against the divider wall to disengage the PC board connectors from one another and permit removal of at least one of the PC boards. A method for disengaging a PC board including a PC board ejector assembly from a chassis is also provided.

Abstract: A method for routing conductors in an integrated circuit design is disclosed, including the steps of determining the number of sensitive conductors requiring placement into quiet track locations, wherein a quiet track location is defined as any track location immediately adjacent to a stable conductor, determining the number of quiet track locations available in said integrated circuit design, and routing one or more sensitive conductors into one or more quiet track locations.

Abstract: An apparatus for reducing the magnitude of an external clock signal is provided wherein the external clock signal is provided on the motherboard of a computer, the signal is provided onto a plug-in CCA, and the signal must pass through a resistive voltage divider prior to being provided to circuits requiring the reduced magnitude signal.