Abstract: A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.

Abstract: A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices.

Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.

Abstract: The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.

Abstract: A distributed file system is disclosed which may include one or more input/output (I/O) nodes and one or more compute nodes. The I/O nodes and the compute nodes may be communicably coupled through an interconnect. Each compute node may include applications to perform specific functions and perform I/O functions through libraries and file system call handlers. The file system call handlers may be capable of providing application programming interfaces (APIs) to facilitate communication between the plurality of I/O nodes and the applications. The file system call handlers may use a message port system to communicate with other compute nodes.

Abstract: Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.

Abstract: Systems and methods for providing mechanically reinforced plated through-holes (PTH) in PCBs, which advantageously allow improved soldering capabilities and reliability, are described herein. Such systems and methods are achieved by reducing the heat sinking effects of PTHs by providing one or more vias surrounding the PTHs to provide an electrical connection between the PTH and the internal and bottom conductive layers of a PCB. In this regard, the PTHs are spaced apart from at least one of the internal conductive layers (e.g., ground or power layers), so the heat sinking effects are reduced. This feature enables molten solder to substantially fill the entire PTH before freezing, thereby improving the mechanical and electrical connection between an electrical component and the PCB. One or more electrically-nonfunctional lands (or “rib reinforcements”) are provided in internal conductive layers to mechanically support the walls of the PCB.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.

Abstract: A mechanism is disclosed for implementing fast locking in a multi-threaded system. This mechanism enables fast locking to be performed even on an operating system platform that does not allow one thread to assign ownership of a lock on a mutex to another thread. In addition, the mechanism performs locking in a manner that ensures priority correctness and is low-memory safe. In one implementation, the priority correctness is achieved by using operating system mutexes to implement locking, and the low-memory safe aspect is achieved by pre-allocating a memory section to each thread. This pre-allocated memory section ensures that a thread will have sufficient memory to obtain a lock, even when a system is in a low-memory state. With this mechanism, it is possible to implement locking in a safe and efficient manner.

Abstract: A cooling system for cooling computer component with a liquid provided at atmospheric pressure, or low pressure, that flows through channel defined in the computer component. The liquid is pumped from a reservoir to a discharge port, or weir, that is located above the computer component. The liquid flows through an in-feed manifold to diverters that direct the liquid into in-feed tanks located above a row of the computer component. The liquid flows through the channels and flow control orifices to a drain that returns the liquid to the reservoir.

Abstract: A method for scheduling a thread on a plurality of processors that includes obtaining a first state of a first processor in the plurality of processors and a second state of a second processor in the plurality of processors, wherein the thread is last executed on the first processor, and wherein the first state of the first processor includes the state of a cache of the first processor, obtaining a first estimated instruction rate to execute the thread on the first processor using an estimated instruction rate function and the first state, obtaining a first estimated global throughput for executing the thread on the first processor using the first estimated instruction rate and the second state, obtaining a second estimated global throughput for executing the thread on the second processor using the second state, comparing the first estimated global throughput with the second estimated global throughput to obtain a comparison result, and executing the thread, based on the comparison result, on one selected fr

Abstract: A system and method of character input using a virtual keyboard, which may have a reduced number of keys. The virtual keyboard may be displayed on a touch screen and may include a plurality of keys. The virtual keyboard may have a plurality of keys, each key having a number of characters or symbols. Characters associated with a particular key may be selected through a series of related touch screen inputs.

Abstract: A computer readable storage medium including executable instructions for heuristics-based task scheduling. Instructions include receiving a first event notification associated with a first event, where the first event is determined from the first event notification. Instructions further include determining whether a predicate for an action is satisfied by the first event, where the action predicate, the action, and an action parameter are associated with a task object in a task pool. Instructions further include obtaining the action parameter when the action predicate is satisfied by the first event, where a priority is assigned using a heuristics policy to the task object based on the action parameter. Instructions further include inserting the task object into a task queue using the assigned priority. The action associated with the task object is performed by an execution thread. The performance of the action is a second event associated with a second event notification.

Abstract: A heat sink for use with a heat generating component includes a molded cooling block including a molded cooling passage for receiving a cooling medium. The cooling block is configured to be positioned in sufficient heat transfer relationship with respect to the heat generating component so that the cooling medium receives heat from the heat generating component.

Abstract: A method including receiving a set of input data in a first matrix format. The method further includes compressing the set of input data to obtain a first set of compressed data in a second matrix format, where compressing the set of input data includes using a quantization equation, the quantization equation including Yq(i,j)=[(Y(i,j)+offset)<<n]/qs, where Yq(i,j) represents a coefficient in a matrix of the first set of compressed data having a coordinate (i,j), Y(i,j) represents a coefficient in a matrix of the set of input data having the coordinate (i,j), offset is an integer, << is a first bit-wise shift operator, n is an integer, qs is a real number. The method also includes sending the first set of compressed data to a first destination.

Abstract: A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Abstract: A computer readable medium comprising software instructions for managing resources on a host, wherein the software instructions comprise functionality to: configure a classifier located on a NIC, to forward packets addressed to a first destination address to a first HRR mapped to a first VNIC, wherein packets addressed to the first destination address are associated with a first PFC lane; configure the classifier to forward packets addressed to a second destination address to a second HRR, wherein packets addressed to the second destination address are associated with a second PFC lane; and transmit, by the first VNIC, a pause frame associated with the first PFC lane to a switch operatively connected to the physical NIC, wherein the switch, in response to receiving the pause frame, stores packets associated with the first PFC lane in a buffer without transmitting the packets.

Abstract: A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node.

Abstract: A value is assigned to a layout bound of a first node in a scene graph. The layout bound constitutes a bounding volume for the object corresponding to the node and may be the display properties of the object and a first set of display modifiers for the node but not a second set. A display layout is calculated for a second node in the scene graph based on the value of the layout bound. Then, nodes of the scene graph are rendered to generate a display on a display device according to the calculated display layout. The value of the layout bound may be assignable, creating greater flexibility in controlling layout. Additionally, the value assigned to the layout bound may be changed. In this way, layout of nodes with respect to each other is flexible and visual effects and animations can either be factored into that layout or not.

Abstract: A D-latch circuit includes a feed forward circuit, a full keeper circuit, and an output buffer circuit. The feed forward circuit inputs a clock signal and a data signal. The feed forward circuit is connected to an input of the full keeper circuit. The feed forward circuit is connected to an output of the full keeper circuit and an input of the output buffer circuit. The output buffer circuit outputs an output signal. The D-latch consists of a single clocked device that switches with the clock signal.