Abstract: A data tree is generated in memory by parsing a first XML file. Default setting requests and validation requests are read from a second XML file. Default data values for nodes in the data tree are generated by executing default data generation code from locations specified in the default setting requests and recorded in the data tree. The content of data stored in nodes of the data tree is then validated by executing validation code from locations specified in the validation requests. The data tree is then searched by getting a nodepath, parsing the nodepath into a plurality of path pieces, searching the data tree based on each of the path pieces, and returning one or more nodes of the data tree based on the search that satisfy the path pieces. A data value of one or more nodes or child nodes may be specified to narrow the search.

Abstract: A method for monitoring communication on a network. The method includes configuring a classifier using a monitoring rule, receiving a plurality of packets from the network; analyzing each of the plurality of packets by the classifier to determine to which of the plurality of packets satisfies the monitoring rule; forwarding any of the plurality of packets that satisfy the monitoring rule to a first hardware receive ring (HRR) located on a first physical network interface (NI), forwarding any of the plurality of packets that do not satisfy the monitoring rule to a second HRR, and transmitting a first number of packets from the first HRR directly to user level memory, wherein the user level memory resides on a host operatively connected to the first physical NI.

Abstract: One embodiment provides a system that mitigates vibrations caused by cooling fans in a computer system. More specifically, the system includes a cooling fan mechanically coupled to the chassis of the computer system, wherein vibrations generated by the cooling fan are coupled to the chassis. The system also includes an actuation mechanism that creates a relative displacement between the cooling fan and the chassis when a control signal is applied to the actuation mechanism. The system additionally includes a detection mechanism which detects the relative displacement and generates a feedback signal which represents the relative displacement. The system further includes a control signal generation mechanism which converts the feedback signal into the control signal, which is subsequently applied to the actuation mechanism. When the control signal is applied to the actuation mechanism, the relative displacement between the cooling fan and the chassis vibrationally decouples the cooling fan from the chassis.

Abstract: Embodiments of a device (such as a computer system or a circuit tester), a method, and a computer-program product (i.e., software) for use with the device are described. These systems and processes may be used to statistically characterize interdependencies between sub-circuits in an integrated circuit (which are referred to as ‘aggressor-victim relationships’). In particular, statistical relationships between the aggressors and victims are determined from values of a performance metric (such as clock speed) when the integrated circuit fails for a group of state-change difference vectors. Using these statistical relationships, a worst-case sub-group of the state-change difference vectors, such as the worst-case sub-group, is selected. This sub-group can be used to accurately test the integrated circuit.

Abstract: A data storage system for use with a plurality of tape cartridges is provided. Each tape cartridge includes a length of tape media and an amount of flash memory. The data storage system includes a tape cartridge library having a plurality of storage cells. Each storage cell is configured to store a tape cartridge. The tape cartridge library further includes a plurality of tape drives. Each tape drive is configured to access a tape cartridge when the tape cartridge is received in the tape drive. The system further includes a robotic tape mover and a flash memory access mechanism. The robotic tape mover moves tape cartridges between the plurality of storage cells and the plurality of tape drives. The flash memory access mechanism is configured in the tape cartridge library to access the flash memory of a tape cartridge when the tape cartridge is in the tape cartridge library.

Abstract: A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter.

Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.

Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.

Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary.

Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.

Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.

Abstract: Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize a time stamp counter (TSC) register of the CPUs in the multiprocessor computer system to detect the clock skew between the various CPUs in the system. Further, the delay between measurements of the TSC registers of the CPUs may be minimized by utilizing the features of the hardware cache control or management protocols of the computer system, thereby providing more accurate clock skew measurements.

Abstract: A mounting plane assembly (e.g., backplane or midplane) is provided for interconnecting a plurality of daughterboards in a server computer. The mounting plane assembly includes a printed circuit board (“PCB”) that has a plurality of shared mounting holes for attaching connector alignment pins to a front side of the PCB as well as mechanical support elements to a back side of the PCB through the same mounting holes.

Abstract: A method for encrypting data includes receiving a block of plaintext for a data set at one or more computers, acquiring a cryptographic key for the data set, generating an initialization vector for the block of plaintext based on the block of plaintext, and encrypting the block of plaintext using the cryptographic key and the initialization vector.

Abstract: A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse.

Abstract: A system for transmitting data, including: a transmitter node having a setup path packet and multiple data packets; a receiver node connected to the transmitter node by a first optical channel (OC); and a first intermediate node having a first forwarding module and connected to the transmitter node by a second OC and to the receiver node by a third OC, where the transmitter node transmits the setup path packet and a first subset of the multiple data packets to the first intermediate node using the second OC, where the first forwarding module relays, in response to receiving the setup packet, the first subset to the receiver node by switching the first subset from the second OC to the third OC, and where the receiver node receives a second subset of the multiple data packets from the transmitter node using the first OC.

Abstract: Embodiments of a system are described. This system includes an array of chip modules (CMs) and a baseplate, where the baseplate is configured to communicate data signals via optical communication. Moreover, the array includes first CMs mechanically coupled to first alignment features on the baseplate, and adjacent second CMs mechanically coupled to second alignment features on the baseplate. In this array, a given first CM is electrically coupled to a given set of electrical proximity connectors. Additionally, the array includes bridge components, wherein a given bridge component is electrically coupled to the second SCM and another set of electrical proximity connectors, which is electrically coupled to the set of electrical proximity connectors, thereby facilitating communication of other data signals between adjacent first CMs and second CMs via electrical proximity communication.

Abstract: Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.

Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.

Abstract: Embodiments of a system are described. This system includes an array of chip modules (CMs) that are configured to communicate data signals with each other via optical communication. In a given CM module, optical signal paths, such as waveguides, are routed in the same way as in the other CMs in the array. In this way, a common optical design in the CMs may be used in the system to prevent data conflicts during the optical communication.