Abstract: A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.

Abstract: Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.

Abstract: A mechanism is disclosed for implementing fast locking in a multi-threaded system. This mechanism enables fast locking to be performed even on an operating system platform that does not allow one thread to assign ownership of a lock on a mutex to another thread. In addition, the mechanism performs locking in a manner that ensures priority correctness and is low-memory safe. In one implementation, the priority correctness is achieved by using operating system mutexes to implement locking, and the low-memory safe aspect is achieved by pre-allocating a memory section to each thread. This pre-allocated memory section ensures that a thread will have sufficient memory to obtain a lock, even when a system is in a low-memory state. With this mechanism, it is possible to implement locking in a safe and efficient manner.

Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

Abstract: A cooling system for cooling computer component with a liquid provided at atmospheric pressure, or low pressure, that flows through channel defined in the computer component. The liquid is pumped from a reservoir to a discharge port, or weir, that is located above the computer component. The liquid flows through an in-feed manifold to diverters that direct the liquid into in-feed tanks located above a row of the computer component. The liquid flows through the channels and flow control orifices to a drain that returns the liquid to the reservoir.

Abstract: A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

Abstract: One or more embodiments of the present invention relate to a method for duplicate virtual function table removal. The method includes identifying, using a processor of a computer, a first virtual function table formed when a first source code is compiled into a first object code. The method further includes using the processor, identifying a second virtual function table formed when a second source code is compiled into a second object code. The method further includes, independent of linking the first object code to a first executable binary code and the second object code to a second executable binary code, identifying, using the processor, that the first virtual function table and the second virtual function table are identical and, using the processor, deleting the second virtual function table.

Abstract: In at least one embodiment, an apparatus for providing resources from a plurality of on-board device nodes to a hot-plugged device node in a computer is provided. The apparatus comprises a resource manager configured to receive a resource request over a bus system indicative of a set of desired resources from the hot-plugged device node. The resource manager is further configured to probe a parent device and at least one upper level device node positioned above the parent device node for the set of desired resources. The resource manager is further configured to provide the set of desired resources from the parent device node and one or more nodes of the at least one upper level device node over the bus system for transmission to the hot-plugged device node to enable the hot-plugged device node to operate in the intended manner.

Abstract: A method for scheduling a thread on a plurality of processors that includes obtaining a first state of a first processor in the plurality of processors and a second state of a second processor in the plurality of processors, wherein the thread is last executed on the first processor, and wherein the first state of the first processor includes the state of a cache of the first processor, obtaining a first estimated instruction rate to execute the thread on the first processor using an estimated instruction rate function and the first state, obtaining a first estimated global throughput for executing the thread on the first processor using the first estimated instruction rate and the second state, obtaining a second estimated global throughput for executing the thread on the second processor using the second state, comparing the first estimated global throughput with the second estimated global throughput to obtain a comparison result, and executing the thread, based on the comparison result, on one selected fr

Abstract: Some embodiments of the present invention provide a system for packet classification and spreading in a virtualized system. The system can use information in a packet's header to determine a destination system-image in the virtualized system, and a packet-spreading policy for the destination system-image. The system can determine a key using the information in a packet's header. Alternatively, the system can hash the information in the packet's header to obtain an index value. Next, the system can use the key or the index value to perform a lookup in a table which associates keys or index values with system images and/or packet-spreading policies. Once the destination system-image and the packet-spreading policy are determined, the system can deliver the packet to a thread on the destination system-image according to the packet-spreading policy.

Abstract: A heat sink for use with a heat generating component includes a molded cooling block including a molded cooling passage for receiving a cooling medium. The cooling block is configured to be positioned in sufficient heat transfer relationship with respect to the heat generating component so that the cooling medium receives heat from the heat generating component.

Abstract: Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed.

Abstract: Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X<R inner checkbits and R?X data bits, and C?2 data-bit columns containing data bits. Note that each column is stored in a different memory component, and the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, the system attempts to correct a column of the block from the failed memory component by using the checkbits and the data bits to produce a corrected column.

Abstract: A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Abstract: A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM.

Abstract: Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict.

Abstract: A single-chip module (SCM) and a multi-chip module (MCM) that includes at least two instances of the SCM are described. The SCM includes a pad disposed on a substrate. This pad has a top surface that includes a pattern of features. A given feature in the pattern of features has a height that extends above a minimum thickness of the pad, thereby increasing a capacitance associated with the pad relative to a configuration in which the top surface is planar. Furthermore, pads disposed on the two instances of the SCM in the MCM may each have a corresponding pattern of features that increases the capacitive coupling between the pads relative to a configuration in which the top surfaces of either or both of the pads are planar. Note that the pads may be aligned such that features in the patterns of features on these pads are interdigited with each other.

Abstract: Some embodiments provide a system that increases parallelization in a computer program. During operation, the system obtains a binary associative operator and a ordered set of elements associated with a prefix operation in the computer program. Next, the system divides the elements into multiple sets of contiguous iterations based on a number of processors used to execute the computer program. The system then performs, in parallel on the processors, a set of local reductions on the contiguous iterations using the binary associative operator. Afterwards, the system calculates a set of boundary prefixes between the contiguous iterations using the local reductions. Finally, the system applies, in parallel on the processors, the boundary prefixes to the contiguous iterations using the binary associative operator to obtain a set of prefixes for the prefix operation.

Abstract: A computer readable storage medium including executable instructions for heuristics-based task scheduling. Instructions include receiving a first event notification associated with a first event, where the first event is determined from the first event notification. Instructions further include determining whether a predicate for an action is satisfied by the first event, where the action predicate, the action, and an action parameter are associated with a task object in a task pool. Instructions further include obtaining the action parameter when the action predicate is satisfied by the first event, where a priority is assigned using a heuristics policy to the task object based on the action parameter. Instructions further include inserting the task object into a task queue using the assigned priority. The action associated with the task object is performed by an execution thread. The performance of the action is a second event associated with a second event notification.

Abstract: A computer readable storage medium including executable instructions for managing a task. Instructions include receiving a request. Instructions further include determining a task corresponding with the request using a request-to-task mapping. Instructions include obtaining a task entry corresponding with the task from a task store, where the task entry associates the task with an action and a predicate for performing the action. Instructions further include creating a task object in a task pool using the task entry. Instructions further include receiving an event notification at the task engine, where the event notification is associated with an event. Instructions further include determining whether the predicate for performing the action is satisfied by the event. Instructions further placing the task object in a task queue when the predicate for performing the action is satisfied by the event.