Abstract: An extensible fingerprint comprised of an ordered list of fingerprints generated by applying each of a plurality of distinct fingerprinting functions to the content of a data item. The extensible fingerprint can be extended by using a new fingerprinting function to compute a new fingerprint and adding the new fingerprint to the list so that the old extensible fingerprint of a data item is used as a prefix of the new extensible fingerprint for that data item. Thus, the fingerprint can be incrementally extended over time. A content-addressed storage system uses extensible fingerprints as addresses and can also change over time.

Abstract: A data tree is generated in memory by parsing a first XML file. Default setting requests and validation requests are read from a second XML file. Default data values for nodes in the data tree are generated by executing default data generation code from locations specified in the default setting requests and recorded in the data tree. The content of data stored in nodes of the data tree is then validated by executing validation code from locations specified in the validation requests. The data tree is then searched by getting a nodepath, parsing the nodepath into a plurality of path pieces, searching the data tree based on each of the path pieces, and returning one or more nodes of the data tree based on the search that satisfy the path pieces. A data value of one or more nodes or child nodes may be specified to narrow the search.

Abstract: A method for enforcing network bandwidth partitioning. The method includes verifying that a guest driver in a guest operating system (OS) is configured to enforce a resource usage policy, wherein the guest OS resides on a host, mapping a hardware receive ring (HRR) residing on a physical network interface card (NIC) operatively connected to the host to the guest OS, wherein after the mapping the guest OS is configured to receive packets directly from the HRR, determining, using monitoring information, that the guest OS should not receive packets directly from the HRR, and in response to the determination, creating a data path from the HRR to a host OS executing on the host, receiving packets for the guest OS from the HRR by the host OS over the data path, and forwarding the packets from the host OS to the guest OS.

Abstract: A method involving receiving an indication of a requirement to allocate at least one page for a process, where pages are associated with cache colors; generating a selection bitmap by performing a logical operation of a system available colors bitmap and a process bitmap, where the system available colors bitmap and the process bitmap each include one bit corresponding to each cache color, where each bit of the system available colors bitmap indicates whether a number of pages associated with a corresponding cache color that are available to be allocated is above a minimum threshold, and where each bit of the process bitmap indicates whether any pages associated with the corresponding cache color have been recently allocated for the process. The method also includes selecting, using the selection bitmap, a cache color; and allocating a page for the process, wherein the allocated page is associated with the selected cache color.

Abstract: A method for loading shared libraries. The method includes receiving an indication of a requirement to load the shared library into the virtual memory and determining that the shared library is a candidate for using shared large pages. Further, the method includes, in response to the determination, storing a text section of the shared library in a shared large page of the virtual memory and storing a data section of the shared library in a page of the virtual memory, where the virtual memory is mapped to a physical memory of the computer, where, within an address space of the virtual memory, a starting address of the text section of the shared library is separated from a starting address of the data section of the shared library by a predefined distance, and where the predefined distance is larger than a size of the large page.

Abstract: A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.

Abstract: A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.

Abstract: A digital voltage regulator including a dual rail delay chain having large size, feed forward cross-coupled inverters that interconnect the two rails. Stages of the delay chain include a dual-ended output that provides a data signal and a substantially simultaneous data complement signal to a flip-flop component associated with a sampling circuit. In use, the enhanced resolution delay chain and the reduced metastability window flop-flop increase the precision of the digital voltage regulator.

Abstract: A mounting plane assembly (e.g., backplane or midplane) is provided for interconnecting a plurality of daughterboards in a server computer. The mounting plane assembly includes a printed circuit board (“PCB”) that has a plurality of shared mounting holes for attaching connector alignment pins to a front side of the PCB as well as mechanical support elements to a back side of the PCB through the same mounting holes.

Abstract: Aspects of the invention are directed to a systems and methods for operating a non-native binary in dynamic binary translation environment. In accordance with an embodiment, there is provided a computer program product in a computer readable medium. The product includes program code for receiving a non-native binary in a computer readable medium and program code for translating the non-native binary. Additionally, the product includes program code for executing the translated non-native binary, the non-native binary including one or more threads, and program code for pausing execution of the translated non-native binary. The product also includes program code for providing guest instruction boundary information to a monitoring process and program code for analyzing a state of each thread of the translated non-native binary.

Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.

Abstract: A delay chain initialization circuit that converts a singled-sided signal to a dual sided-signal. The dual-sided delay chain including a data rail and a complement rail. Each of the data rail and data complement rail include inverter chains that are interconnected through cross-coupled inverter pairs. The delay chain initialization circuit being adapted to produce, at an output, a data signal and a data complement signal that are substantially simultaneous.

Abstract: A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse.

Abstract: A method for routing a chip, involving forming a plurality of nets configured to connect components of the chip, wherein each of the plurality of nets is included in a netlist, assigning at least one repeater to each of the plurality of nets in the netlist, wherein the repeaters are assigned prior to performing physical routing of the plurality of nets, inserting the at least one repeater in a corresponding net, wherein the insertion of the at least one repeater divides the corresponding net into at least two subnets, and performing the physical routing of the plurality of nets by connecting each of the subnets.

Abstract: In some embodiments, a content server receives a request for a widget from a web server, specifying a user identifier and a delegation server. If the delegation server is trusted, the user's identity is ascertained using the user identifier. The widget is delivered having a context of the user's identity. The content server receives a request to access content generated utilizing the widget incorporated into a web page and allows access based on the context of the widget. In other embodiments, a social network server receives a request from a web server for a widget. The widget is delivered having a source indicator. Subsequently, the social network server receives a request to access the social graph generated utilizing the widget incorporated into a web page. If the request includes a change to the social graph, the social network server allows the request if the widget is trusted.

Abstract: Methods and apparatuses are disclosed for testing multicore processors. In some embodiments, the tested multicore processor may include at least a first core and a second core, a data input coupled to a first scan chain in the first core and a second scan chain in the second core, and a multiplexer including at least a first input and a second input, the first input coupled with a data output of the first scan chain and the second input coupled with a data output of the second scan chain, the multiplexer further including an output that couples to one or more pins on a package of the processor, the multiplexer further including a select signal that couples to the one or more pins on the package of the processor, and wherein the data input couples to the one or more pins on the package of the processor.

Abstract: In embodiments, prior to compilation into machine code, a preprocessor generates directives by processing a source code and/or bytecode representation of a program and/or selecting default directives. The preprocessor embeds the directives in a bytecode representation of the program or a separate stream associated with the bytecode representation of the program. A just-in-time compiler may compile the bytecode representation into machine code directed by the embedded directives in one pass and/or a bytecode interpreter may interpret the bytecode representation of the program. In some embodiments, a computing device generates bytecodes during execution of a program, selects default directives, and embeds the default directives in the bytecodes or a separate stream associated with the bytecodes prior to compilation of the bytecodes into machine code.

Abstract: A semiconductor die includes: a clock distribution network that distributes a clock signal within the die. The clock distribution network includes: a clock tree corresponding to one or more metal layers of the die, a plurality of clock spines corresponding to a metal layer of the die, a plurality of clock wings corresponding to a metal layer of the die, a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die, a clock grid placed in the one or more gaps of the floorplan, a plurality of buffers placed in a local gain buffer pair configuration wherein the local gain buffer pair connects the clock grid to a shorting bar, and a plurality of conductors that connect the shorting bar to a plurality of loads.

Abstract: A garbage collector determines a target amount of heap space to deallocate, estimates an amount of heap space reachable by a plurality of soft references by determining a cumulative size of no more than an exploration bound N number of objects reachable from each soft reference, and deallocates heap space based on the target amount and the estimate of the heap space reachable from the soft references. Deallocating heap space may include clearing at least one soft reference. If the estimate is inaccurate, it may be utilized regardless or modified to account for inaccuracy. The least-recently-used or the largest soft reference may be cleared until the total cleared space reachable exceeds the target amount. By performing a bounded analysis, the garbage collector may be able to make a more informed decision about whether to clear a soft reference without consuming the full amount of resources consumed by an exhaustive analysis.

Abstract: Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection.