Abstract: Scrolling through one or more focusable and/or non-focusable items may be accomplished by: scrolling the display a set number of pixels in said direction if the cursor location is on a non-focusable item and an end border in said direction of said non-focusable item is not currently shown on the display; moving the cursor location to a next focusable item in said direction and scrolling the display enough in said direction to display said next focusable item if the cursor location is on a non-focusable item and an end border in said direction of said non-focusable item is currently shown on the display or if the cursor location is on a focusable item and a next item in said direction is a focusable item or if the cursor location is on a focusable item, the next item in said direction is a non-focusable item, and an end border in said direction of said non-focusable item is currently shown on the display; and moving the cursor location to a next non-focusable item and scrolling the display in said direction if

Abstract: System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.

Abstract: The present invention provides a system and method for reading a SRAM unit having a first SRAM way and a second SRAM way with a read control system, a way select macro and a word select macro. The word select control macro is configured to select one of the plurality of words. The way select control macro is configured to select either the first SRAM way or the second SRAM way. The system and method employ a read logic controller having a word select function and a way select function. The read logic controller is operatively coupled to a read counter, a word counter, and an address counter.

Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Abstract: A circuit board assembly that includes a circuit board. The circuit board includes a plurality of electrical contacts. The circuit board assembly also includes a solder cover that covers the electrical contacts. The solder cover includes a cover and a sliding-flange that is coupled to the cover. The circuit board assembly includes a retainer for restraining the solder cover. The retainer includes a mounting-flange and a retaining-flange.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: One embodiment of a storage controller is described including a controller memory, one or more central processing units (CPUs), and a host bus adapter all coupled to a controller bus. The one or more CPUs are configured to produce data routing information dependent upon a data transfer command which directs a transfer of data between a host computer and one or more storage devices. The host bus adapter includes a receive unit and a transmit unit adapted for coupling to a transmission medium. The host bus adapter receives the data routing information, and forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory.

Abstract: An interface for a distributed processing framework (DPF) is disclosed. The distributed processing framework (DPF) can manage the execution of a process utilizing cross-platform dynamically networked distributed computer system. The interface to the distributed processing framework (DPF) can be implemented as a graphical user interface. The graphical user interface allows users to conveniently communicate with the distributed processing framework. The graphical user interface can provide users with customized menus. Accordingly, the user can conveniently make selections and submit a request for processing.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: A method allocates computing resources from a resource pool. Each job request includes attributes and a unique identifier. A digital signature is generated for each job request based on the combination of the attributes. The identifier is associated with the digital signature. Job requests having identical attributes are grouped together.

Abstract: An enhanced Java Bytecode verifier suitable for operation in a Java computing environment is disclosed. The enhanced Java Bytecode verifier operates to determine whether one or more Java conventional Bytecode commands within a stream of Bytecodes are likely to place a reference to a Java object on the execution stack. In one embodiment, the conventional Java Bytecode commands identified as such are translated by the enhanced Java Bytecode verifier into one or more corresponding Java commands. When a corresponding command is executed, the reference associated with the conventional Java command is placed on a reference stack as well as the execution stack.

Abstract: We introduce obstruction-freedom—a new non-blocking condition for shared data structures that weakens the progress requirements of traditional nonblocking conditions, and as a result admits solutions that are significantly simpler and more efficient in the typical case of low contention. We demonstrate the merits of obstruction-freedom by showing how to implement an obstruction-free double-ended queue that has better properties than any previous nonblocking deque implementation of which we are aware. The beauty of obstruction-freedom is that we can modify and experiment with the contention management mechanisms without needing to modify (and therefore reverify) the underlying non-blocking algorithm. In contrast, work on different mechanisms for guaranteeing progress in the context of lock-free and wait-free algorithms has been hampered by the fact that modifications to the “helping” mechanisms has generally required the proofs for the entire algorithm to be done again.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: A shielding apparatus for containing electromagnetic energy is disclosed. In one embodiment, a shield includes a plurality of sides, each side having a top and a bottom. A flange may extend from the top of the sides. A plurality of tabs extend from the flanges. The tabs include a first, second, and third portions. The first portion extends directly from the flange. The second portion extends at an angle from the first portion relative to the plane of the first portion and the flange. The longitudinal axis of the second portion is parallel to its associated flange or side. A third portion extends from the second portion, at an angle relative, to the second portion. A heat sink coated with an electrically conductive material may be mounted such that a bottom side of the heat sink is in contact with the plurality of tabs.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: A system and method for providing dynamic class reloading using a modular, pluggable and maintainable class loader is described. Each application in an application server (or alternatively in any implementation) may include a dynamic class loader module. The class loader module may include a hierarchical stack of class loaders. Each module in the application may be associated with its own class loader. Each class loader may be responsible for loading one or more classes. When a class is changed, the changed class may be detected by the class loader module. Any notification for a class change may come to the class loader controller so that the concerned class loader can be replaced. The class loaders for all classes that depend on the changed class may also be replaced. The replaced class loaders may then reload the affected classes.

Abstract: An existing neutral operating system (OS) signal is utilized to notify a virtual machine (VM) about a change to its execution parameters. The signal is predefined to indicate that an execution parameter should be changed, and upon receipt, the VM may look up a file in a predefined location, the file containing the new command line parameters. The VM may then modify its parameters to match the file, and continue with its execution, thus providing a mechanism for altering VM execution parameters at runtime.

Abstract: Provided is a method, system, program, and data structure for applying a patch to a computer system, wherein the patch includes content to add to the computer. A computer object is generated to include configuration information on the determined installed components. At least one patch includes content to add the computer and is capable of being associated with at least one realization, wherein each realization defines a state of the computer. For each realization, a determination is made from the configuration information in the computer object as to whether the state defined by the realization exists in the computer. Data is written to the computer object indicating whether the state defined by the realization exists on the computer. The computer object is used to determine whether each patch is compatible with the installed components of the computer.