Abstract: An efficient method is described for laying out a table for display. The method may be used to display tables on a small footprint device, such as a smart cellular phone, a personal data assistant, a handheld computer, etc. Small footprint devices typically have smaller displays than other computing systems such as desktop computers. In one embodiment the method is employed to lay out HTML tables in a web browser running on a small footprint device.

Abstract: A module and a corresponding connector that include multiple rows of contacts is described. In one embodiment, the module may include a channel formed in a bottom edge of the module. A plurality of contacts may be disposed on the inner surface of the channel and the outer surface of the module. A complementary connector is also described.

Abstract: Apparatus and methods for achieving a desired value of electrical impedance between parallel planar conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the planar conductors. The methods include bypass capacitor selection criteria and electrical resistance determination criteria based upon simulation results. An exemplary electrical power distribution structure produced by one of the methods includes a pair of parallel planar conductors separated by a dielectric layer, n discrete electrical capacitors, and n electrical resistance elements, where n≧2. Each of the n discrete electrical resistance elements is coupled in series with a corresponding one of the n discrete electrical capacitors between the planar conductors. The n capacitors have substantially the same capacitance C, mounted resistance Rm, mounted inductance Lm, and mounted resonant frequency fm-res.

Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

Abstract: Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.

Abstract: In general, the invention relates to a method for optimized execution of a computer program including detecting a preservable static field in said computer program with a compiler, comprising detecting at least one selected from the group consisting of a getstatic instruction and a putstatic instruction, annotating said preservable static field to create an annotation indicating whether said field is preservable, compiling said computer program to produce an output using said annotation, wherein said output includes information about said field, encoding said output if backward compatibility is required, loading said output, and executing said output in an environment.

Abstract: A registry service is described which uses a partitioned publisher assertion recording and accessing scheme. A publisher assertion regarding a relationship between entities (e.g., business or other types of entities) is encoded within a directory information tree in a memory. The publisher assertion includes publisher assertion part nodes corresponding to entity nodes in the directory information tree. The publisher assertion is complete if all publisher assertion parts corresponding to entities in the relationship are present in the directory information tree. The service may include a network including directory servers and registry servers. The publisher assertions are manipulated by authorized publishers and accessed by users using a variety of techniques, the operations of which are performed by such parties and/or are encoded upon computer-readable media.

Abstract: A buffer block allocation table as well as a buffer allocation table may be provided to handle a buffer request in a system management controller. When a buffer request is received, the buffer block allocation table may be scanned entry-by-entry to find an available buffer block. once one its located, it is marked as taken. Then, the corresponding buffer block in the buffer allocation table is scanned entry-by-entry looking for one that is available. If one is found, it is used for the buffer request. If one cannot be found, the system may return to the buffer block allocation table and continue with the next entry. This process may repeat until an available buffer is found.

Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.

Abstract: In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of registers is an extended register having multiple storage locations. Values stored in the multiple storage locations are accessed, for example, according to the order in which they have been stored. Less than all of the multiple storage locations are accessible by a register operation at a given time. Older versions of software that do not recognize extended registers identify the extended register as having only one storage location. An extended register can be, for example, a stack register, a queue register, or a mixed register and values stored in the multiple storage locations are read and stored according to the characteristics of the register.

Abstract: A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node.

Abstract: A present invention discloses an automated method to generate an eye-plot for signals produced by a simulation or captured hardware results. The automated approach is customizable in that the designer may specify input parameters to customize the analysis to fit the needs of the user. The eye-plot is then generated. The eye-plot may be output on the printer, displayed on the video display or even stored in secondary storage for subsequent review and use.

Abstract: Managing a task in a system management controller may be accomplished by storing information regarding the task in a process control buffer. A state of the task stored in the process control buffer may be examined to determine if it is active. If so, then a task counter contained in the process control buffer can be examined to determine if the task should be run immediately, or at a later time. If it is immediately, the task is immediately executed. If not, then timer fields may be examined to determine precisely when the task should be executed. The task counter may also indicate the number of times the task should be executed, or if it should be executed indefinitely. Thus, the method may be restarted with a new process control buffer if the timer fields are not less than or equal to a current time.

Abstract: A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.

Abstract: An information processing system includes a runtime versioning facility which allows for managing its configuration so that modifications made during runtime are propagated and take affect without restarting the system or a portion thereof. This allows the potential for 100% uptime while upgrading such systems. This also provides a system capability to process multiple configuration versions, and to be able to process such versions even while such versions are changing during operation of the information processing systems. For example, a system such as a registry server capable of transactional configuration changes is provided which manages its configuration so that modifications made during runtime are propagated and take affect without restarting the server.

Abstract: A circuit for a plus one operation includes a means for incrementing a first bit set of a binary number and a means for detecting a zero in any bit set less significant than the first bit set, the means for detecting being coupled to the means for incrementing. The means for incrementing operates in a first mode when the means for detecting detects a zero in any bit set less significant than the first bit set and operates in a second mode when the means for detecting does not detect a zero in any bit set less significant than the first bit set.

Abstract: A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.

Abstract: A method for optimizing loop bandwidth in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and the loop bandwidth of the phase looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a phase locked loop is provided.

Abstract: Methods and apparatus for deleting a member in a circular singly linked list are described. Just prior to the current pointer register being updated, its contents are copied to the previous pointer register. When the consumer needs to delete a member from the list, the previous member location is known because it is saved in the previous pointer register. In this way, deletions done at the time of scanning involve only a single SRAM write access since the contents of the current pointer register is copied into the member referenced by the previous pointer register.

Abstract: A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.