Abstract: A mobile agent may be provided for collaborative content control in peer-to-peer networks. A peer may launch a mobile agent including an itinerary of peers to be visited and indications of one or more documents that the peers are collaboratively editing. The mobile agent may visit peers indicated by the itinerary to collect version information for the document(s). The mobile agent may return the version information to the initiating peer, which may coordinate each of the document(s) on the peer to a most recent version in accordance with the version information provided by the mobile agent. Visited peers may use the payload to determine if their version of the document(s) are up to date and, if not, may add a version update request to the payload. The initiating peer may send the most recent version information to peers that added version update requests to the payload.

Abstract: In accordance with the invention, a data storage system for storing and retrieving fixed data content includes: a storage system network; one or more peer node computer systems interconnected by the storage system network; and at least one disklet stored on at least one of the one or more peer node computer systems, the disklet for execution on the data storage system using data that are stored on, being written to, or being read from the data storage system. In one embodiment, a disklet includes executable program code and a disklet interface that permits the program code of the disklet to be loaded on to the data storage system and executed on the data storage system by a user.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: A computer assembly for example for use as a network server comprises housing a host processor located within the housing and, a service processor also located within the housing for providing system management functions within the computer assembly. The housing includes a display that is located thereon for displaying the status of components of the assembly obtained from the service processor, and one or more manual switches located on the housing for enabling a user to vary information displayed by the display and/or to alter the status of the equipment. The computer assembly may include a console interface that communicates with the service processor to enable the system management functions of the assembly to be monitored and/or the status thereof to be modified from a remote console connected thereto in addition to or instead of by the display and switches.

Abstract: A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link; and de-packetizing the even-sized packets to reform the even number of odd-sized packets. Re-packetizing may involve dividing each of the even number of odd-sized packets into an even-sized portion and a remaining portion. Each even-sized portion may be transferred as one of the even-sized packets. The remaining portions of each of the even number of odd-sized packets may be combined to form another one of even-sized packets. De-packetizing may involve associating each of several portions of one of the even-sized packets with a respective other one of the even-sized packets.

Abstract: Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cache memory and by designing the replacement algorithm of the on-chip cache memory such that only one line in a given set maps into an off-cache memory cache line, the frequency of off-chip cache memory accesses may be greatly reduced, thereby improving performance and efficiency.

Abstract: The method and apparatus for analysis of integrated circuits using static timing analysis. For a circuit being analyzed, the value of the state net for the case of an undriven sensitization is resolved to a Hi/Lo logic on the output net and the sensitization is added to the appropriate pull-up/pull-down function on the output net. Furthermore, in the sensitization generation, the “present” state logic function at the output net is determined by the “previous” state variable of the sequential state net and the “present” state variables of the rest of the inputs to the sequential circuit. The “next” state logic function at the output net is determined by the “present” state variable of the sequential state net and the “next” state variables of the rest of the inputs to the sequential circuit. This variable is resolved as a function of “previous” state net variable and “present” state input net variables.

Abstract: A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a storage including a plurality of entries configured to store corresponding snoop filter indications. The mechanism also includes a cache controller configured receive a transaction request including an address and to generate an index for accessing the storage by performing a hash function on the address. The cache controller selectively generates a snoop operation to the cache memory for the transaction request dependent upon a snoop filter indication stored in the storage that corresponds to the address.

Abstract: A low overhead method for identifying memory leaks is provided. The low overhead method includes a) detecting completion of a garbage collection cycle; and b) identifying a boundary between used objects in memory and free memory space. The steps of a) and b) are repeated and then it is determined if there is an existing memory leak based upon evaluation of boundary identifiers. A computer readable media and a system for identifying memory leaks for an object-oriented application are also provided.

Abstract: A method for determining clock skew to avoid hold time violations is provided. The method includes obtaining a total delay to a source by adding a first delay associated with each of the delay elements in a clock tree path leading to a source. The method also includes obtaining a total delay to a destination by adding a second delay associated with each delay element in a clock tree path leading to a destination. Thereafter, a source sum delay of the delay elements in the clock tree path leading from the source to a common point is obtained. Similarly, a destination sum delay is obtained for the delay elements in the clock tree path from the destination to the common point. Subsequently, the actual delay to the source is obtained by subtracting the source sum delay from the total delay. Similarly, actual delay to the destination is obtained by subtracting the destination sum delay from the total delay.

Abstract: An information processing system is provided. The information processing system comprises: an information processing subsystem including a processor and a processor support chip in data communication therewith. The processor support chip is operable to provide processor support functions for the processor, and comprises a local management entity. The system further comprises a remote management entity connected to communicate with a remote management network. The local management entity is connected to communicate with the remote management entity via a first management communication channel; and the local management entity is operable to monitor the remote management entity and, in response to detection of an error status of the remote management entity, to divert management communications to a second management communications channel bypassing the remote management entity to maintain communications with the remote management network.

Abstract: A security architecture has been developed in which a single sign-on is provided for multiple information resources. Rather than specifying a single authentication scheme for all information resources, the security architecture associates trust-level requirements with information resources. Authentication schemes (e.g., those based on passwords, certificates, biometric techniques, smart cards, etc.) are employed depending on the trust-level requirement(s) of an information resource (or information resources) to be accessed. Once credentials have been obtained for an entity and the entity has been authenticated to a given trust level, access is granted, without the need for further credentials and authentication, to information resources for which the authenticated trust level is sufficient.

Abstract: A integrated circuit housing includes a first clamping hardware, a second clamping hardware operatively connected to the first clamping hardware, and an integrated circuit stack comprising a top portion and a bottom portion, wherein the first clamping hardware contacts the top portion and the second clamping hardware contacts the bottom portion, and wherein a first shim is interposed between the bottom portion and the second clamping hardware.

Abstract: A computer system having a user specified web browsing system for selectively retrieving content from a variety of web sites is disclosed. The web browser of the present invention is configured to track multiple web sites at any given time to determine content updates in these web sites. In one embodiment of the present invention, the web browser automatically periodically checks user specified web sites, detects changes to content at these web sites, filters out unimportant changes and delivers a summary of the changes to the user.

Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.

Abstract: A method for processing packets that includes receiving a first packet for a first virtual machine by a network interface card (NIC), classifying the first packet using a hardware classifier, where the hardware classifier is located on the NIC, sending the first packet to a first one of a plurality of receive rings based on the classification, sending the first packet from the first one of the plurality of receive rings to a first virtual network interface card (VNIC), sending the first packet from the first VNIC to a first interface, and sending the first packet from the first interface to the first virtual machine, where the first virtual machine is associated with the first interface, where the first VNIC and the first virtual machine are executing on a host.

Abstract: A method for processing packets that includes receiving a first packet for a first target by a network interface card (NIC), classifying the first packet, sending the first packet to a first receive ring in the NIC based on the classification of the first packet, sending the first packet to a Network Layer from the first receive ring, sending a first virtual network stack (VNS) Instance ID associated with the first receive ring to the Network Layer, obtaining a first VNS Instance parameter using the first VNS Instance ID, and processing the first packet in the Network Layer using the first VNS Instance parameter to obtain a first network processed packet.

Abstract: A method for notifying a packet destination that includes receiving a packet by a network interface card (NIC), where the packet destination is a destination of the packet, classifying the packet, forwarding the packet to one of a plurality of receive rings on the NIC, determining whether the one of the plurality of receive rings comprises space to store the packet, dropping the packet if the receive ring does not comprise the space to store the packet, and sending a notification message to the packet destination, where the notification message indicates that the packet was dropped by the receive ring.

Abstract: A method for changing network configuration parameters that includes generating a request to change a network configuration parameter by a user, determining whether the user is allowed to change the network configuration parameter using a network configuration database, if the user is allowed to change the network configuration parameter, updating the network configuration database to reflect the change in the network configuration parameter, updating a container associated with the network configuration parameter to reflect the change in the configuration parameter, and if the user is not allowed to change the network configuration parameter, dropping the request.

Abstract: A method for processing a packet that includes receiving a packet for a target, classifying the packet, and sending the packet to a receive ring based on the classification. The method also includes obtaining an identifier (ID) associated with the target based on the classification, and sending a request for virtual memory that includes the ID. Furthermore, the method includes determining, using the ID, whether the target has exceeded a virtual memory allocation associated with the target. In addition, the method includes allocating the virtual memory, storing the packet in the virtual memory, and updating the virtual memory allocation associated with the target to reflect the allocation of the virtual memory, all if the target does not exceed the virtual memory allocation. The method further includes waiting until the target is not exceeding the virtual memory allocation if the target exceeds the virtual memory allocation.