Abstract: A digital communication system is presented including at least one transmission line coupled between a first and second communication devices and used to convey binary data from the first communication device to the second communication device. A termination resistor and one end of the transmission line are coupled to an input node of the second communication device. An electrical voltage level existing at the input node of the second communication device may be substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced. Three or more different voltage levels may be present upon the transmission line dependent upon the binary data.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.

Abstract: A system that measures timing margins within a digital system by varying a clock skew between components in the digital system. The system receives a reference clock signal as an input. This reference clock signal is used to generate a first clock signal and a second clock signal so that there exists a programmable skew between the first clock signal and the second clock signal. The first clock signal is used to drive a first component, and the second clock signal is used to drive a second component in the digital system. The system measures an upper margin for the clock skew by iteratively increasing the clock skew and testing the system to verify that it operates correctly. When the digital system stops operating correctly, the upper margin is set to be the amount by which the clock skew was increased before the digital system stopped operating correctly.

Abstract: The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e.g., for a cache miss, dirty data in the main cache is merged with modified data from an associated write cache, and the resultant writeback data line is loaded into a writeback buffer. The writeback data is also written back into the main cache, and is maintained in the main cache until replaced by new data. Subsequent requests (i.e., snoops) for the data are then serviced from the main cache, rather than from the writeback buffer. In some embodiments, further modifications of the writeback data in the main cache are prevented. The writeback data line in the main cache remains valid until read data for the cache miss is returned, thereby ensuring that the read address reaches the system interface for proper bus ordering before the writeback line is lost.

Abstract: A program interpreter for computer programs written in a bytecode language, which uses a restricted set of data type specific bytecodes. The interpreter, prior to executing any bytecode program, executes a bytecode program verifier procedure that verifies the integrity of a specified program by identifying any bytecode instruction that would process data of the wrong type for such a bytecode and any bytecode instruction sequences in the specified program that would cause underflow or overflow of the operand stack. If the program verifier finds any instructions that violate predefined stack usage and data type usage restrictions, execution of the program by the interpreter is prevented. After pre-processing of the program by the verifier, if no program faults were found, the interpreter executes the program without performing operand stack overflow and underflow checks and without performing data type checks on operands stored in operand stack. As a result, program execution speed is greatly improved.

Abstract: A model of a LSSD storage element and non-LSSD storage element interface for use with an automatic test pattern generator has been developed. The model includes a master element, a slave element, and a master observe module. The master observe module alternatively selects the input signal for the master element and the output signal from the slave element.

Abstract: A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result, the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: One embodiment of the present invention provides a system for viewing plurality of objects on a display that allows a user to zoom on a non-positional display attribute of the plurality of objects. The system operates by receiving a value for a mapped attribute for an object as well as a value for a zooming parameter for the non-positional display attribute. The system maps the mapped attribute to the non-positional display attribute for the object by computing a function of the value of the mapped attribute and the zooming parameter to produce a value for the non-positional display attribute. If the value for the zooming parameter changes in a first direction, the function maps a narrower range of mapped attribute values to prominent display attribute values. If the value for the zooming parameter changes in a second direction, the function maps a wider range of mapped attribute values to prominent display attribute values.

Abstract: Apparatus, methods, and computer program products are disclosed for a process of terminating a thread in a clean, certain, and forcible manner. A thread is forcibly terminated in such a manner that data structures in the system are not left in an inconsistent state and the overall system status is not damaged. The methods and systems described are for terminating a thread in a computer language execution environment. Methods are implemented in an interpretive loop executing in a language that is interpreted and in runtime support libraries in a language that are not interpreted. A method of forcibly terminating a thread in a computer language execution environment is described. A thread receives a terminate thread command. The thread has associated with it a termination flag, a value of the termination flag being immutable once set, and one or more monitors. The termination flag is then set for the thread.

Abstract: The data type of requested data stored in a column of a database table is determined and the data accessed in the data type in which the data is stored. The data type can then be converted to a second data type before outputting the data.

Abstract: The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.

Abstract: Described is a scheduling system that provides allocation of system resources of one or more processor sets among groups of processes. Each of the process groups is assigned a fixed number of shares, which is the number that is used to allocate system resources among processes of various process groups within a given processor set. The described fair share scheduler considers each processor set to be a separate virtual computer. Different process sets do not share processes, a particular process must execute on a single processor set. In another embodiment of the invention, each process group could be given a separate number of shares for each processor set. Percentage of the resources of the specific processor set allocated to processes of a process group is calculated as a ratio of the shares of the process group on the processor set to the total number of shares of active process groups operating in that set.

Abstract: The header inscription of one or more columns in a data table is reduced in horizontal width. A user having input to a first view of a data table can select a desired column at any location in the column to reduce the horizontal width of the header inscription. The header inscription is reduced in horizontal width, and a second view of the data table is displayed in which the header inscription of the selected column has reduced horizontal width. The header inscriptions of some or all columns in the data table can also be reduced in horizontal width by selection of a single column. Further, the header inscription style utilized in the reduction of the horizontal width can be user selected.

Abstract: Provided is a method, system, program, and data structures for indexing object oriented objects in an object oriented database. an object data structure is provided including a plurality of object oriented objects, wherein each object includes a key value, and wherein each object is associated with an object index. A node data structure is provided including nodes, wherein each node represents one object in the object store and includes one object index used to access the object represented by the node in the object store. The nodes in the node data structure are organized according to the key values in the objects represented by the nodes. The node data structure is used to access the objects in the object store.

Abstract: An apparatus is disclosed for storing electronic devices. The apparatus includes an enclosure, a carrier adapted to contain a peripheral device, and a rotatable attachment between the carrier and the enclosure. The carrier may be rotated from an installed position to an open position. When in the installed position, a long axis of the carrier is substantially parallel to a front of the enclosure. When in the open position, the long axis of the carrier is substantially perpendicular to the front of the enclosure.

Abstract: A network includes routers which route message packets among devices, thereby to facilitate transfer of information thereamong. Each router node makes use of routing information that identifies, inter alia, addresses and address ranges for which other router nodes are responsible, that the respective router node uses in routing a message packet that it receives. Each router node, through a negotiation operation with other router nodes, attempts to aggregate addresses for which it is responsible into one or more address ranges which do not overlap with addresses for which the other router nodes are responsible, and provides the address range(s), along with addresses for which it is responsible which could not be so aggregated, to the other router nodes for use as their routing information. Several methodologies are described for use in connection with the negotiation operations.

Abstract: A computer driven hand held business card printer contains in memory a plurality of different language versions in which the card is printed is selectable, prior to printing. A plurality of different types of cards each with plural language versions may be accommodated. Card content in the various languages is downloadable from a PC into the business card printer using an infrared communications link.

Abstract: A variety of methods and apparatus for managing deactivation and deletion of objects and server processes are taught. According to some embodiments of the present invention, a thread of execution termed the reaper thread systematically cycles through a computer process deactivating and/or deleting objects based upon a variety of criteria. One suitable criterion for object deactivation is based upon the amount of time lapsed since a client has requested services of the object. According to the timeout criterion, the reaper thread determines the period of time since the last client requested services from the object, compares this to a timeout value which may be defined by any suitable entity, and proceeds with deactivation and/or deletion accordingly. Object deletion may have a separate criterion or be specifically requested by a client. A deletion flag may be set to indicate that object deletion is requested.

Abstract: Methods and apparatus for implementing an atomic monitor wait operation are disclosed. According to one aspect of the present invention, a computer-implemented method for implementing an atomic monitor wait operation includes creating a semaphore specific to a first thread. The semaphore is then placed in a wait queue associated with an object whose object lock is owned by the first thread in order to, in one implementation, preserve queue order. The first thread then exits a monitor associated with the object by, in one embodiment, releasing the object lock. The first thread then suspends execution until the semaphore receives notification that the object lock is available.