Abstract: A new interface and methods allow a new versatility both in both managing a database, and in presenting hierarchical database information in a more useful way. User marks are used to determine the visibility of the elements at the various hierarchical levels in a hierarchical directory structure of a database. Hence, the user marks are user hierarchical visibility marks. The user hierarchical visibility marks are automatically propagated to other elements in the structure according to a filter selected by the user, for example.

Abstract: A system including a rendering engine, a sample buffer and a filtering unit. The rendering engine is configured to render samples in response to received graphics data. The sample buffer is configured to receive and store the samples. The filtering unit is configured to read and filter the samples stored in the sample buffer to generate pixel values. The filtering unit includes a counter controller, a set of positive counters and a set of negative counter. The counter controller is configured to accumulate a histogram of exponent values of the pixel values in the positive counters and negative counters. The positive counters maintain count values for exponents of positively signed pixel values and the negative counters maintain count values for exponents of negatively signed pixel values.

Abstract: The present invention involves a system and method for performing motion estimation. For each candidate motion vector, encoding distortion is determined between a macroblock and a reconstructed macroblock by determining discrete cosine transform cofficients of the macroblock and quantizing the discrete cosine transform coefficients. An estimate unit determines the length of the bit stream required to encode the quantized discrete cosine transform coefficients along with the mode information bits including mode and motion vector information. The reconstructed macroblock is determined based on the quantized discrete cosine transform coefficients. A bit-rate term based on the length of the bit-rate stream is determined and included in the encoding distortion. The candidate motion vector which minimizes the encoding distortion of the macroblock is chosen to be the motion vector for the macroblock.

Abstract: A system and method for discovering nodes in an M×N torus interconnection fabric of nodes is provided. The method comprises probing an M×N torus interconnection fabric, wherein M and N are integer values and said interconnection fabric includes a first plurality of nodes forming an x-axis and a second plurality of nodes forming a y-axis; and identifying a location of a first node relative to the x and y axes. The computer system comprises an M×N array of nodes, wherein M and N are integer values; and a plurality of interconnects connecting the M×N array. A first plurality of nodes in the M×N array form an x-axis in the M×N array, a second plurality of nodes in the M×N array form a y-axis in the M×N array, and a first node in the M×N array is configured to probe the M×N array to identify a location of the first node relative to the x-axis and the y-axis.

Abstract: An editor or software engineering tool may be configured to render whitespace between adjacent tokens, wherein the amount of whitespace between any two adjacent tokens is determined according to language-specific style rules and scaled in accordance with display considerations. In some realizations, the operative scaling is selected or defined by a user according to the user's visual preferences. In some realizations, the operative scaling relates to requirements or constraints of an automated layout mechanism. For example, a particular scaling may be calculated to adjust line length in conformance with a desired margin alignment or to optimize layout when long lines are automatically wrapped (or folded) in some automatic way.

Abstract: A processor performs precise trap handling for out-of-order and speculative load instructions. It keeps track of the age of load instructions in a shared scheme that includes a load buffer and a load annex. All precise exceptions are detected in a T phase of a load pipeline. Data and control information concerning load operations that hit in the data cache are staged in a load annex during the A1, A2, A3, and T pipeline stages until all exceptions in the same or earlier instruction packet are detected. Data and control information from all other load instructions is staged in the load annex after the load data is retrieved. Before the load data is retrieved, the load instruction is kept in a load buffer. If an exception occurs, any load in the same instruction packet as the instruction causing the exception is canceled. Any load instructions that are “younger” than the instruction that caused the exception are also canceled.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array index is less than zero or greater than the size of the array. Three extensions of a boundary check instruction are provided, with each performing a different combination of three boundary check comparisons. One comparison compares a first operand, which may contain the base address of an array, to zero. Another comparison evaluates the value of a second operand, which may contain an index offset, to determine if it is less than zero. The other comparison evaluates whether the value of the second operand is greater than or equal to a third operand. The third operand may indicate the size of an array. A trap is generated if any of the comparisons evaluates to true.

Abstract: A computer system includes a chassis with a single motherboard supporting at least one processor module. A power sub-system receives three power supply units and distributes power within the computer system. Each of the three power supplies has a power rating such that two of the three power supplies are sufficient to power the computer system. The combination of such a single-motherboard-based design with a redundant three-power supply sub-system provides reliability of operation in a cost-effective manner. The power sub-system includes a power distribution board with power distribution logic operable to distribute power from the power supply units for powering the processor module. The power distribution logic is operable to interrupt power for powering the processor module when two of the power supply units fail or are not present. An alarm sub-system is provided for reporting power supply faults.

Abstract: The invention noninvasively provides information relating to memory space allocation. Memory space allocation information is maintained in a location that is known or identifiable outside of the process for which the memory space has, been allocated. A memory space allocator maintains the information in a descriptor block. The descriptor block is updated with every allocation or deallocation of memory space. In the preferred embodiment of the invention, the descriptor block exists on a page of memory having a size equal to the native page size of the machine on which it is, operating. The memory allocator allocates memory space in units referred to as buckets that exist within a memory block. The descriptor block contains an identifier that identifies the memory space allocation information stored in that descriptor block as being controlled by a particular memory space allocator. The descriptor block also contains information that indicates how many pages are used and how many pages are free.

Abstract: A computer system housing with a curved bezel that forms one or more sideways gap between a side of the computer housing chassis and the bezel attached to that side. Typically, the curved bezel is attached to the front of the chassis with each sideways gap extending perpendicularly from the front of the chassis to a predetermined width and stretching to predetermined length along the front of the chassis. The sideways gaps facilitate increased air inlet from the sides and allow efficient cooling of various system components that are mounted on the chassis and housed within the housing. One or more cooling fans may be mounted at different locations within the housing to optimize air circulation and, hence, cooling within the housing. The chassis may be partitioned into two separate sub-chassis for proper positioning of the cooling fans as well as to accommodate changes in computer system configurations with minimized retooling of the chassis.

Abstract: The present invention relates to a garbage collector that uses an LRU algorithm to free memory from an XML DOM tree active in an application cache. According to one or more embodiments of the present invention, a threshold for the amount of memory permitted to reside in an application cache is set. Then, a garbage collector removes entries from the cache until it falls below the threshold. In one or more embodiments, a node table is used. When nodes are added to the XML DOM tree in the application cache the node table is updated. When the threshold for the amount of memory permitted to reside in the application cache is exceeded, the garbage collector applies an LRU algorithm uses the node table to determine which nodes to remove from the application cache. In one embodiment, the LRU algorithm scans the node table to determine the least recently used node in the table by examining time stamp entries in the table.

Abstract: A grammar to represent a hierarchical object-oriented database. The grammar comprises a set of keywords and a syntax. The keywords include “tree”, “entry”, “properties”, and “attributes”. Properties and attributes are defined by name-value pairs. The grammar is designed to be platform-independent and programming-language-independent and therefore descriptive of any hierarchical object-oriented database. A grammatical form, a description of an object-oriented database in a textual form according to the grammar, may be stored in a persistent form such as one or more files on disk. The grammatical form is human-readable and human-editable. The grammatical form can be created by hand, or it can be created from an object-oriented database in transient form through the process of serialization. The grammatical form can be transformed into an object-oriented database through the process of compilation.

Abstract: A method and apparatus for performing distributed object mapping in a Java language environment includes creating a first object associated with a first language environment and a second object associated with a second language environment. At least one of the objects is a native or legacy object-oriented language object.

Abstract: A processor includes logic for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB), a load buffer asynchronous interface, an external memory management unit (MMU) interface, and others. A processor includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, “pollution”, or “cross-talk” between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.

Abstract: A mechanism for managing a plurality of profile data structures including a plurality of profile objects having an interface for sending and receiving information and a profile service mechanism having an interface for sending and receiving information. A protocol layer operatively coupled to the profile objects interface and the profile service interface, the protocol layer defining a plurality of request elements and a plurality of response elements. A protocol layer interface within the protocol layer receives user-entity specified set of request elements from the user entity and sends a responsive set of response elements to the user entity. A first set of methods within the profile service mechanism that create instances of the profile objects, where each of the first set of methods correspond to one of the request elements and one of the response elements.

Abstract: A method of concurrently performing a component test with returning test result data in a distributed environment is disclosed. In general, in order to assure compatibility of the various components in an enterprise computing system, a service test is created as part of a compatibility test suite and passed to a test application server having a test application program. The test application program makes an initial connection to the component being tested that, in response, creates a connection to a logging listener. The logging listener spawns an acceptor corresponding to the component being tested. Once spawned, the component returns test data to its corresponding acceptor concurrently with the execution of the test.

Abstract: A method of and system for control of access to add an event notification as a log record in a computer system. Each potential log record is associated with one or more logs, each of which has one or more log owners. Grant of access to add a log record to the information in a particular log is restricted to the owner(s) of that log. A list of owners of a log can be changed from time to time, based upon present circumstances or the presence of special conditions.

Abstract: A mechanism is disclosed for implementing multiple thread pools in a computer system to optimize system performance. In accordance with the invention, a plurality of thread pools is initially allocated within a process space, with each thread pool comprising one or more threads. Each thread pool has a set of characteristics associated therewith, and the characteristics of each thread pool are customized for one or more particular types of service. After the thread pools have been allocated, the system receives one or more requests. When a request is received, it is processed to determine with which thread pool the request is to be associated. This processing is carried out by determining the type of service being requested by the request, and then determining which thread pool is associated with that type of service. Alternatively, this processing is carried out by extracting a set of indication information (e.g.

Abstract: A shielded riser card assembly for reducing electromagnetic radiation from a computer enclosure is disclosed. The riser card assembly comprises a four-layer riser card having a connector adjacent its lower edge, such as a connector for an NLX system board. A cable connection socket is on the riser card a first distance away from the connector, and a plurality of traces on a surface of the riser card run between the cable connection socket and the connector. A sheet of conductive material covers the plurality of traces and is spaced a second distance apart from the surface of the riser card. At least one fastener connected is to the sheet and attached to the riser card. The fastener conductively connects the sheet of conductive material to a ground layer of the riser card. A plurality of non-conductive spacers are disposed between and in contact with both of the sheet and the riser card, for maintaining the sheet a predetermined distance away from the riser card.