Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. Calculation of the mean time to failure can include the current density and the temperature. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit based on temperature effects. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: Rendered wire frame models of objects offered for sale can be downloaded and displayed as virtual objects in the context of an environment in which a real object would be actually used. The rendered models are located and oriented so that they appear exactly as a real object would appear when placed in the environment. A video camera captures the environment and a two dimensional perspective view of the rendered wire frame model is combined with an image of the environment to show how the object will look when actually installed.

Abstract: A system generates an audio signature for a data item based on a source identifier associated with the data item. The system receives a source identifier along with a data item and maps the source identifier to the audio signature using a mapping function that allows a user to distinguish the audio signature from other audio signatures generated for other sources. The mapping functions always map the same source identifier to the same audio signature. The system outputs the audio signature to a user. This enables the user to associate the audio signature with the source. The data item can include, an electronic mail message, a pager signal, a telephone call, a data item in an instant messaging system, an indicator of an entry of a new participant into a conference call or a chat room, or an electronic cookie that identifies a client computer system to a web site.

Abstract: An apparatus for multiplying a first number and a second number together is described, each of the numbers having a width of 8, 16, 32, 64 or 128-bits or more. The 32-bit embodiment of the apparatus includes a booth recorder having two inputs and 16 outputs, the recorder determining 16 individual booth groups associated with the second number and providing one partial product per booth group on individual ones of the 16 outputs.

Abstract: In a compression system, three-dimensional geometry is first represented as a generalized triangle mesh, a data structure that allows each instance of a vertex in a linear stream to specify an average of two triangles. Individual positions, colors, and normals are quantized, preferably quantizing normals using a novel translation to non-rectilinear representation. A variable length compression is applied to individual positions, colors, and normals. The quantized values are then delta-compression encoded between neighbors, followed by a modified Huffman compression for positions and colors. A table-based approach is used for normals. Decompression reverses this process. The decompressed stream of triangle data may then be passed to a traditional rendering pipeline, where it is processed in full floating point accuracy.

Abstract: A multiple compressor refrigeration heat sink module is suitable for use in standard electronic component environments. The multiple compressor refrigeration heat sink module is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system. As a result, the multiple compressor refrigeration heat sink module can be utilized in existing electronic systems without the need for significant system housing modification or the “plumbing” associated with prior art liquid-based cooling systems. The multiple compressor refrigeration heat sink module is also well suited for applications that require a highly reliable, energy and space efficient, cooling systems for electronic components such as multi-chip modules and mainframe computer applications.

Abstract: A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis and having a second opening, wherein the first opening and the second opening are generally aligned. The apparatus further includes a backplate covering the aligned first opening and second opening.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.

Abstract: The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a particular embodiment, the semiconductor device is a multi-chip semiconductor that comprises a first semiconductor device and a second semiconductor device. The first semiconductor device has a first surface. The first surface contains a first ridge alignment member and a second ridge alignment member, the first and second ridge alignment members forming a receiving area between the first and second ridge alignment members. The second semiconductor device has a second surface, the second surface containing a third ridge alignment member, the second semiconductor device positioned such that at least a portion of the third ridge alignment member is located within the receiving area of the first semiconductor device.

Abstract: A dynamic sense amplifier is provided that reduces the amount of time required to perform a memory cell restoration in a DRAM following a read operation. The dynamic sense amplifier can be isolated from the bit lines that it is sensing to avoid the capacitance affects of the bit line during a restoration operation. By avoiding the capacitance effects of the selected bit line during a restoration operation the dynamic sense amplifier is able to restore the just read memory cell to its original state in a more efficient manner.

Abstract: A system and method for calculating a deadlock-free set of paths in a network which generates an ordered set of deadlock-free sub-topologies, referred to as “layers.”The ordered set of layers is used to determine a deadlock-free set of paths through the network. The resulting paths allow data to be efficiently routed through the network without causing traffic to be disproportionately routed through any subset of links. Each of the deadlock-free layers may be any type of deadlock-free sub-topology. The generated ordering may be any arbitrary ordering of the layers. A shortest-path route calculation is performed with the following constraint: starting at any given layer, for each node, proceed to calculate a shortest path to every other node in the graph where at any node being utilized to assess a given minimum path, the path may move to any higher-ordered layer, but may never return to a lower ordered layer. In this way, within each layer, a path moves through a tree and thus avoids deadlock.

Abstract: A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor stage in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.

Abstract: A network adapter includes a bypass buffer with sufficient capacity to store a packet from an upstream neighboring adapter and to store at least one additional incoming packet as a local packet is sent. The adapter also includes control logic which monitors the bypass buffer to determine whether the adapter may send local data packets. A network may be formed of such network adapters linked through counterrotating rings. If the control logic determines that the bypass buffer has sufficient storage available to avoid overflow while the adapter sends the local packet, the adapter sends the local packet. The control logic may choose to send a local packet only if there is sufficient room available within the bypass buffer to store a packet the same size as the local packet which is to be sent, thereby insuring that the bypass buffer does not overflow before the adapter can resume transmitting data from the bypass buffer.

Abstract: A method and apparatus for pre-processing and packaging class files. Embodiments remove duplicate information elements from a set of class files to reduce the size of individual class files and to prevent redundant resolution of the information elements. Memory allocation requirements are determined in advance for the set of classes as a whole to reduce the complexity of memory allocation when the set of classes are loaded. The class files are stored in a single package for efficient storage, transfer and processing as a unit. In an embodiment, a pre-processor examines each class file in a set of class files to locate duplicate information in the form of redundant constants contained in a constant pool. The duplicate constant is placed in a separate shared table, and all occurrences of the constant are removed from the respective constant pools of the individual class files.

Abstract: An operating system call control subsystem is disclosed for use in a computer that includes a processor for processing a program, the program instructions of an operating system call instruction type identifying one of a plurality of types of operating system calls, each type of operating system call being associable with an operating system call type identifier value within a predetermined range of values. The operating system call control subsystem comprises a crossover table, an operating system call instruction type address resolution module, and an operating system call instruction type processing module. The crossover table has a number of entries corresponding to a predetermined fraction of the predetermined range, each entry in the crossover table having an instruction for enabling the processor to save a value corresponding to an offset of the entry into the crossover table.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: A garbage collector collects a train-managed heap in accordance with the train algorithm. In doing so, it concentrates into a respective train the heap-located objects that belong to garbage cycles even if those cycles additionally include certain types of objects that are outside the train-managed heap. It does so by using objects within the heap as proxies for those extra-heap objects, and it evacuates into a proxy object's train any collection-set objects referred to by the extra-heap objects for which the proxy object is a proxy. The objects in those garbage cycles containing the extra-heap objects can thereby be collected incrementally despite the extra-heap references to them.

Abstract: A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.