Abstract: The present invention is directed to a sorber which is suitable for use in an electromagnetic wave activated sorption system and which is easily adaptable to packaging constraints. One embodiment of the sorber comprises a flexible enclosure having an outer conductor, and inner conductor, a port through which a sorbate can be communicated into and out of said enclosure, and a sorbent in the enclosure which can adsorb the sorbate to form a sorbate/sorbent compound. The enclosure is configured to be coupled to an electromagnetic wave generator so that waves generated by the electromagnetic wave generator propagate through the sorbate/sorbent compound within the enclosure. Another embodiment of the sorber comprises an enclosure which is configured to serve as a structural component.

Abstract: A dynamic flip-flop circuit that operates in a pre-charge phase and an evaluation phase allows for implementation of multiple-input logic functions without sacrificing performance by using a single evaluation path to generate its output signals. In one embodiment, the dynamic flip-flop circuit includes input logic that receives a clock signal and one or more data input signals. The clock signal defines the pre-charge phase and the evaluation phase of the flip-flop circuit. The input logic has an output terminal connected to a first output buffer circuit, which in turn drives the flip-flop circuit's Q output signal. The output terminal of the input logic is combined with the clock signal in a logic gate having an output terminal connected to a second output buffer circuit, which in turn drives the flip-flop circuit's complementary output signal {overscore (Q)}.

Abstract: A method and circuit which allow for pre-emphasis of a high frequency on-chip signal have been developed. The circuit is configured to receive a digital signal from an on-chip source as input for a predriver stage. The method and circuit may use a dual or single predriver stage to equalize the signal when a transition in the value of the digital signal is detected. The single predriver stage circuit equalizes the signal with decreased power and area requirements for greater efficiency.

Abstract: A decoder is used in an end-to-end scalable video delivery system operable over heterogeneous networks. The decoder may software-based and computationally low complexity, or may be implemented inexpensively in ROM hardware. The system utilizes a scalable video compression algorithm based on a Laplacian pyramid decomposition to generate an embedded information stream. At the receiving end, the decoder extracts from the embedded stream different streams at different spatial and temporal resolutions. Decoding a 160×120 pixel image involves only decompressing a base layer 160×120 pixel image. Decoding a 320×240 pixel image involves decompressing and up-sampling (e.g., interpolating) the base layer to yield a 320×240 pixel image to which is added error data in a first enhancement layer following its decompression.

Abstract: Access to external service providers is provided through portlets, where each portlet accessible by a user is represented on the display of the user device. Through use of a dynamic content channel, e.g., a portlet, a highly customizable content page may be produced for any individual client system. When a portlet is selected on a user device, the content associated with the portlet is retrieved and automatically transformed into data that can be displayed by that user device. Thus, a particular user device is not limited to accessing content in a format identical to that associated with the user interface in use on the user device. Consequently, the user's ability to access a wide variety of content sources independent of the characteristics of the particular user device is further enhanced. An individual user can personalize the user device by specifying which service providers from among the ones the organization has made available via portlets, the user wants to use.

Abstract: An adaptive memory control determines optimal values for the refresh period and row and column address strobe signal frequency of an associated DRAM. A binary test pattern is written to the DRAM array, read during a subsequent read operation, and then compared to the original test pattern. If a match, the 1's complement of the test pattern is written to the array and then compared as described above with the original 1's complement pattern. If a match, the process is repeated using a more aggressive value for the desired parameter, i.e., refresh period, strobe frequency, etc. If at any point the comparison does not result in a match, a more conservative parameter value is used for the subsequent write, read, and compare sequence. This process continues until an optimal value for each desired parameter is determined.

Abstract: A data processing apparatus is described which comprises a microprocessor having data lines, address lines and control lines, a memory interface having input control lines, input address lines, output control lines, and output I/O lines wherein one or more input address lines of the memory interface are coupled to an equal number of address lines of the microprocessor. Further, a memory having control lines and I/O lines is provided, the control lines of the memory being coupled to output control lines of the memory interface, and I/O lines of the memory being coupled to output I/O lines of the memory interface. The memory receives command, data and address information through the I/O lines.

Abstract: A message dispatch system is provided for a multi-computer server having a number of server computers connected via respective server network links. The message dispatch system, which is connectable to an external telecommunications network, includes a message dispatcher configured to receive external client requests for the multi-computer server from the external telecommunications network and to dispatch the client requests to selected server computers via the server network links. The message dispatcher is configured to determine a server to which an external client request is to be dispatched in response to parameters representative of message traffic volume on the server network links. Load balancing is performed based on parameters representative of the server network link loading, rather than, or possibly in addition to measurements on processor loading. Suitable network loading parameters can be derived by monitoring packets passing from and/or to the individual server computers.

Abstract: A method and system for leasing storage locations in a distributed processing system is provided. Consistent with this method and system, a client requests access to storage locations for a period of time (lease period) from a server, such as the file system manager. Responsive to this request, the server invokes a lease period algorithm, which considers various factors to determine a lease period during which time the client may access the storage locations. After a lease is granted, the server sends an object to the client that advises the client of the lease period and that provides the client with behavior to modify the lease, like canceling the lease or renewing the lease. The server supports concurrent leases, exact leases, and leases for various types of access. After all leases to a storage location expire, the server reclaims the storage location.

Abstract: Apparatus, methods and computer program products permit a decision to record time sequential information, beginning at a particular point in time, to be made after that particular point in time. In one implementation, a decision to record a piece of music from the beginning can be made anytime during the playing of the music. In others, a decision to record a video program from the beginning can be made during the program. In a portable video camera, a decision to save a boy's turn at bat can be made after he hits a home run.

Abstract: A system and method for securing a program's execution in a network environment is presented. A first server is configured to permit execution of a program from a second server based on a configurable security characteristic of the program. The first server receives the program transferred from the second server. Subsequently, the program is checked for the configurable security characteristic. The program is executed on the first server if permitted by the configurable security characteristic.

Abstract: A method and apparatus for identifying an applicant as a member of a group without explicitly listing all possible applicants. A test is defined which specifies the criteria for group membership. The test definition and an optional group identifier code are supplied to a criterion generator. The criterion generator generates an authenticated message based, at least in part, upon said test definition. The authenticated message is delivered to one or more criterion evaluators that verify the authenticated message. In one embodiment, once the authenticated message has been verified, the applicant for access to a resource presents a credential to the criterion evaluator. If the credential satisfies the test definition, the applicant is granted access to the specified resource and denied access if the credential does not satisfy the test definition.

Abstract: Systems and methods for rendering a complex character suitable for display on a monitor are provided. A raw character bitmap representing the complex character is filtered to form a filtered bitmap so as to reduce the effects of monitor flicker and enhance image contrast. The filtered bitmap is then scaled down to a target bitmap using a bilinear scaling operation followed by recursive cubic scaling operations. The target bitmap is suitably sized for storage in a memory device coupled to the monitor.

Abstract: A bootstrap system for a computer with peripheral devices has a first level boot firmware program and a second level boot program loaded from disk by the first level program. The second level boot program contains a device tree constructed according to IEEE-1275 (Open Firmware) standards, describing currently known peripheral devices and computer resource allocations. The device tree is modifiable during boot operations to incorporate information about additional devices. The second level boot program scans I/O buses for additional devices not included in the current device tree and loads drivers only for the additional devices. The second level boot program further allows a user to enter information into the device tree. The second level boot program is preferably implemented under DOS emulation, and may be developed in a DOS-based code development environment and ported to the computer.

Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: The invention is a method and apparatus for chording. One embodiment of an apparatus comprises a user-wearable support element, in the form of a glove having finger and thumb portions. An output generating element in the form of a switch is provided corresponding to each finger and thumb portion of the glove. An activator is provided for each finger and thumb portion of the glove. In one embodiment, each activator comprises a wire having one end connected to the glove and a second end arranged to activate the switch corresponding to its respective finger or thumb portion. Movement of each finger and thumb into one or more positions causes the respective activator to activate its respective switch. In one embodiment, the outputs generated by the switches are input to a signal controller. The signal controller is arranged to provide a second output dependent upon the inputs from the various switches. In one embodiment, the second output is determined from a map and comprises alphanumeric data.

Abstract: A power sub-system controls the supply of power to a field replaceable unit. The power sub-system includes a main power controller that supplies main power to at least a first component of the field replaceable unit, and a standby power controller that supplies standby power to at least a second component of the field replaceable unit. The main power controller is operable to switch off the supply of main power to a first component in response to the detection of a fault, whereas the standby power controller maintains the supply of standby power to the second component. By providing separates power controllers for main and standby power, it is possible to maintain power to one or more selected components of the FRU in the event of a fault that requires main power to the FRU to be cut. Standby power is switched off automatically in response to a first change in state of an interlock signal that is indicative of the field replaceable unit being released.

Abstract: In a superscalar processor, multiple instructions are executed in parallel to obtain multiple execution results, and the multiple execution results are stored in a working register file. Each execution result in the working register file has at least one status bit associated therewith which identifies the execution result as valid data. The multiple execution results contained in the working register data then retired by changing the status bits associated with each execution result to identify the execution result as final data. In this manner, the speculative data is retired as the final data without data movement of the speculative data, thus reducing a number of ports needed in the superscalar processor.

Abstract: A method and system for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. A system controller provides dedicated transaction request queues and controls the forwarding of transactions from a processor to a slave. The transaction requests are automatically forwarded to an intended slave on the same address bus as the system controller immediately. The system controller determines whether the proper criteria are met for that slave to receive such a request, such as the slave's request receive queue is not full and that global ordering requirements are met. If so, then on a separately provided line, the system controller validates the request for immediate reception by the slave.

Abstract: A client enabled to load and run Java applets in a distributed object computing system retrieves needed Java classes in a location-independent manner from various class servers in the system. Initially, the client queries a naming service of the distributed object computing system to determine the class server that contains the base class needed. A connection through an object request broker is made from the client to the class server. The client then requests the code for the base class from the class server by using the object request broker. The class server retrieves the code by either reading a file from its own local file set, or if the code is not local, queries the naming service for another class server that has access to the code for the base class. This process of finding a class server and determining if the code is local may be recursive as classes may be moved or renamed. The class server then returns this code to the client by way of the object request broker.