Abstract: A system for presenting hypermedia link information. A computer-implemented method for presenting hypermedia link information is described which relates to the user the characteristics of a data file pointed to by the hypermedia link. The computer system waits for an event to occur. This event is the user or system selecting one or more hypermedia links. The hypermedia link in this scenario points to a data file about which information is to be gathered. The computer system then requests information about the data file. Finally, an auditory cue is generated to communicate information about said data file to a user. Alternatively, this information may be conveyed to the user by visual means, such as a pop-up information box on the user's display. A powerful and convenient system for browsing hypermedia information is thus provided.

Abstract: Authentication and session management can be used with a system architecture that partitions functionality between a human interface device (HID) and a computational service provider such as a server. An authentication manager executing on a server interacts with the HID to validate the user when the user connects to the system via the HID. A session manager executing on a server manages services running on computers providing computational services on behalf of the user. The session manager notifies each service in a session that the user is attached to the system using a given HID. A service can direct display output to the HID while the user is attached to the system. When a user detaches from the system, each of the service's executing for the user is notified via the authentication manager and the session manager. Upon notification that the user is detached from the system, a service can continue to execute while stopping its display to the HID.

Abstract: A memory has memory cells arranged in rows and columns. The memory cells of each row are coupled to a word line that is separate from word lines connecting to the memory cells of other rows. Each column has mutually exclusive subsets of memory cells. The memory cells are coupled to bit lines. Each bit line is coupled to a selected mutually exclusive subset of memory cells. The memory cells of a selected row output a cell voltage on the coupled bit lines when the coupled word line is asserted. A multiplexor receives the cell voltages on the bit lines. The multiplexor is responsive to column select signals to select one of the columns as a selected column, and outputs a multiplexor voltage corresponding to the cell voltage of the memory cell of the selected row and the selected column.

Abstract: A system for providing a double compare and swap operation is disclosed. In the disclosed system, a first single compare and swap operation is performed. If a contents of a first variable is equal to an old value for the first variable, then the first compare and swap operation writes a value to the first variable indicating that the variable is not accessible and indicates success. A second single compare and swap operation is executed in the event that the first single compare and swap operation indicates success. If a contents of a second variable is equal to an old value for the second variable, then the second single compare and swap operation writes a new value for the second variable into the second variable and indicates success. If the second single compare and swap operation indicates success, a new value for the first variable is written to the first variable.

Abstract: A dynamic compiler determines whether to inline methods in place of virtual method calls by inspecting such calls' receiver expressions. If a given call site meets other criteria for inlining, the method is inlined if its receiver expression can be proved to have a property called “pre-existence.” One kind of expression whose pre-existence is easily proved is a calling-procedure argument to which the body of the calling procedure makes no assignment. One of the other criteria is that the argument's static type is a class whose definition of the callee method has not been overridden, and the compiler employs a dependency data structure to record against both the caller and the callee that the caller contains code whose validity depends on the assumption that this criterion has been met.

Abstract: A computer apparatus with user and kernel level memory regions schedules multiple light weight processes to run on one or more data processors. A mutex protects data in memory and permits only one thread to access the data at a time. Data pertaining to the running status of each of the light weight processes is stored in one or more kernel data structures which are mapped to the user level. When a thread attempts to acquire a mutex held by another thread, then the kernel data structure is checked to determine the status of the light weight process and its associated thread. The thread attempting to acquire the mutex is caused to sleep or spin according to the current running or not running status of the light weight process. If the light weight process holding a mutex is running, then the thread attempting to acquire the mutex will spin. If the light weight process then holding a mutex is stopped, then the thread attempting to acquire the mutex will block or sleep until awakened.

Abstract: Cooling liquids such as fluorocarbons are enclosed within a module containing electronic components on a printed wiring board. Preferably top and bottom covers are applied to the top and bottom of the board and liquid-sealed thereto. Hot-melt adhesive is used for the seal. Each edge of a top cover has an outward-extending flange formed with a peripheral downward turned lip. Heated adhesive is applied to the cover in a continuous bead around the flange, the thickness of the bead being greater than the height of the lip. The cover is then squeezed against the board so that the adhesive seals against the board and the flange. The bottom cover is formed in complementary fashion.

Abstract: A clip assembly tool for grasping the finger and legs of a retainer and spreading them apart from one another includes a lower arm having a first clasp and an upper arm having a second clasp. The lower arm is pivotally attached to the upper arm. The tool further includes a wedge arm having a nose, where the wedge arm is pivotally attached to the upper arm. To use the tool, the second clasp is moved away from the first clasp and the retainer is inserted between the first and second clasps. The second clasp is then moved back towards the first clasp. The nose of the wedge arm then wedges the legs and finger of the retainer in first and second catchs of the first and second clasps, respectively. The second clasp is then again moved away from the first clasp. Since the legs and finger are securely fastened to the first and second catches, respectively, the finger is spread from the legs.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintain geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus.

Abstract: One embodiment of the present invention provides a system that allows an I/O request to proceed when a primary server that is processing the I/O request fails, and a secondary server takes over for the primary server. Upon receiving an I/O request from an application running on a client, the system stores parameters for the I/O request on the client, and sends the I/O request to the primary server. Next, the system allows the application on the client to continue executing while the I/O request is being processed. If the primary server fails after the I/O request is sent to the primary server, but before an I/O request completion indicator returns from the primary server, the system retries the I/O request to the secondary server using the parameters stored on the client. The I/O request may originate from a number of different sources, including a file system access, an I/O request from a database system, and a paging request from a virtual memory system.

Abstract: A system for coupling a Dynamic Termination Logic (DTL) type output driver to IEEE 1149.1 boundary-scan circuitry includes a logic circuit that converts the data and output enable signals of the IEEE 1149.1 specification to test “q_up,” “q_dn” and “q25_dn” signals meeting the requirements of the DTL driver. These test q_up, q_dn and q25_dn are selectively provided to the DTL driver during boundary-scan testing of the output driver. In a further refinement, the system also converts functional q_up, q_dn and q25_dn signals provided by the circuit under test to the data and output enable signals of the IEEE 1149.1 specification. The system allows the widely used IEEE 1149.1 boundary-scan standard to be used with DTL drivers. The resulting compatibility simplifies the testing and use of the DTL drivers, and provides a new boundary-scan standard for use with DTL drivers that is compliant with the IEEE 1149.1 standard.

Abstract: A system optimizes representation of associations in an object-oriented programming environment. The system includes a memory and a memory manager. The memory stores a table and a plurality of objects. Each of the objects includes a header that stores a flag. The table stores a plurality of entries. Each of the table entries stores an association and a reference identifying one of the objects in the memory. The memory manager periodically determines the state of the flags in the object headers. When the flag of an object is determined to be in a predetermined state, the memory manager selects the table entry having a reference identifying the object and stores the association from the selected table entry into the object.

Abstract: A method and apparatus for managing computer network services from a central management console program residing on an administration server is disclosed. A service, such as an e-mail program, is installed, typically by a system administrator, on a host server computer. During installation, data relating to the service's management module is stored in a well-known location on the host server computer. A central management console program residing on an administration server causes the retrieval of the data relating to the management module from the well-known location. The central management console program stores the data relating to the management module in a storage area accessible by the console program and the host server computer and thereby facilitates the management and modification of the service from the central management console program.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: A method for routing a conductive path in an integrated circuit is described. The method includes providing a side exiting bus comprising at least one pin, and providing a plurality of functional units, at least one functional unit having a pin required to be electrically connected to a pin in the side-exiting bus. The method further includes routing a first conductive path from one of the at least one pins in the side exiting bus to a point external to the functional units, the resulting conductive path spanning the width of the plurality of functional units, and routing a second conductive path in a straight line from the at least one pin in the at least one functional unit to a point on the first conductive path.

Abstract: An MOS device has source and drain regions of a first conductivity formed in a well of a second conductivity, the well of the second conductivity being formed in an upper surface of a bulk material of the first conductivity. Source and drain potentials are applied to the source and drain regions, respectively, while a separate bias potential is routed to the well through a conductive sub-surface layer of the second conductivity which is located spaced from and beneath an upper surface of the bulk material and which is shorted to the well.

Abstract: A method for flushing the data cache in a microprocessor. A central processing unit in the microprocessor is used to perform an operation on a first address stored in a stack cache, the address being associated with a first cache line in a data cache memory. The result of the operation is left on the top of the stack in the stack cache as a second address. A first valid bit associated with the first cache line is changed from a valid setting to an invalid setting during the same clock cycle of the microprocessor in which the operation is performed.