Abstract: A method and apparatus for providing plug-in media decoders. Embodiments provide a “plug-in” decoder architecture that allows software decoders to be transparently downloaded, along with media data. User applications are able to support new media types as long as the corresponding plug-in decoder is available with the media data. Persistent storage requirements are decreased because the downloaded decoder is transient, existing in application memory for the duration of execution of the user application. The architecture also supports use of plug-in decoders already installed in the user computer. One embodiment is implemented with object-based class files executed in a virtual machine to form a media application. A media data type is determined from incoming media data, and used to generate a class name for a corresponding codec (coder-decoder) object.

Abstract: Packets from multiple packet streams are transmitted in an output stream having substantially equally spaced packets using a scheduler which spaces the packets based upon the input stream speeds of the various input streams as well as the bandwidth of the transmission channel. Such a scheduler advantageously spaces the packets so that the maximum distance between two filled slots is never more than twice the minimum distance between any two filled slots. Such a system also advantageously allows the computation of the slot locations to be precomputed when the slots are initially allocated to streams, thereby allowing the scheduler to efficiently compute slot locations while the scheduler is receiving the input streams.

Abstract: A giga-bit interface convertor module bracket assembly having upper and lower ground springs. The upper ground spring has upper wing-shaped springs in the upper part of the front opening of the bracket assembly and a pair of upper spring tabs on the interior of the bracket assembly. The lower ground spring has lower wing-shaped springs in the lower part of the front opening of the bracket assembly and a pair of lower spring tabs on the interior of the bracket assembly. When a giga-bit interface convertor module is inserted in the bracket assembly through the front opening, the upper and lower spring tabs bias against the top and bottom walls of the giga-bit interface convertor module to provide grounding thereto. Additionally, the upper and lower wing-shaped springs contact with a front panel of an enclosure or bracket or an electronic card on which the bracket assembly sits. The lower ground spring is provided with a bottom ground spring to contact the electronic card for grounding.

Abstract: Electrical resonances are reduced and noise propagation is attenuated in a multi-layer construction using planar power and ground planar conductors separated by insulating material by loading the power and ground planar conductors with a sufficient amount of capacitance, or series capacitance and resistance, at specific locations so that the planar conductors are electrically broken up into smaller sections which resonate at frequencies above the signal bandwidth. The propagation of injected noise is suppressed by the low-pass filter effect of the capacitive loading at the discrete locations. In accordance with one embodiment of the invention, islands of material with a dielectric constant higher than the dielectric constant of the overall insulator are placed at regular intervals where the capacitance of each high dielectric constant island is comparable to, or higher than, the capacitance of the “low” dielectric material which comprises the remainder of the insulating material.

Abstract: A module for a modular system includes requirement indicators defining features of a component required for the module to operate, capability indicators defining features provided by the module and ability indicators defining features of the component acceptable to the module. The combination of the requirements, compatibility and ability indicators provides a very flexible structure for indicating and testing requirements and capabilities in that it permits the designation of requirements, capabilities and the capability to accept inverted capabilities. A variable number of the requirement, capability and ability indicators can be provided to accommodate future requirements. Verification logic is operable to determine compatibility when defined relationships between the requirement, capability and ability indicators for the module and an interconnected component are met. One of the module and the component can be a system component such as a mother board.

Abstract: A system and methods are provided for storing and validating electronic tickets for multiple venues on a single smart card. In accordance with this present embodiment, an operating system of the smart card includes a Java Virtual Machine and an applet loader key. A shared applet, including a venue loader key, is validated with the applet loader key and is stored on the smart card. One or more venue applets are also stored on the smart card, each with a venue key corresponding to an associated venue. Each venue applet is validated by the applet loader key and the venue loader key. The shared applet is used by the venue applets to interface with ticket loaders and ticket validation devices. Tickets are purchased for events associated with the venue applets and are stored on the smart card in association with the related venue applets. Ticket signatures are authenticated with each venue applet's venue key. A ticket is cancelled after being tendered to gain admittance to an event.

Abstract: A memory extension mechanism for a computer printer or other computer output device. The mechanism allows the computer printer to function with less than the maximum amount of real memory normally required by the computer printer in processing a print job. When the computer printer runs low on the amount of memory available, a portion of real memory of the printer containing infrequently used data is copied through a network to a computer's file system storage. The portion of the real memory containing the infrequently used data is then cleared and made available for other uses by the computer printer. When the piece of memory that was previously copied through the network is subsequently needed, it is copied through the network back into the computer printer's real memory.

Abstract: A system and method are presented for stabilizing the electrical impedance of a structure (e.g., an electrical interconnecting apparatus) including a pair of parallel planar conductors separated by a dielectric layer. The structure may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. An electrical resistance connected between the planar conductors about a periphery of the structure serves to stabilize the electrical impedance of the structure, thereby reducing an amount of electromagnetic energy radiated from the structure. The electrical resistance may be multiple discrete electrical resistances dispersed about the periphery of the structure, and the structure need not be rectangular. For example, a portion of the periphery of the structure may define a curve. A general method for stabilizing the electrical impedance of the structure includes selecting a spacing distance.

Abstract: Methods and systems for compressing and decompressing 3-D geometry data which includes regularly tiled surface portions. One compression method includes representing a surface portion as a “vertex raster”, which comprises specifying an extent value and encoding the vertex parameter values of vertices within the surface portion. The extent of the surface portion specifies the arrangement of vertices within the surface portion, and allows the vertices to be properly assembled into drawing primitives during decompression. The encoded vertex parameter values may be encoded globally (by setting initial values and corresponding delta values), locally (on a per-vertex basis), or using a combination of these techniques. Absolute, delta encoding, or delta-delta encoding may be utilized for these parameter values. Vertex parameters which may be encoded in this manner include position, color, normals, z-displacement values, texture map coordinates, and surface material properties.

Abstract: A system that allows a programmer to insert instructions into a computer program that change criteria used by a logic analyzer to gather data. This criteria may include, a qualifier, which is used to filter data gathered by the logic analyzer, or a trigger condition that is used by the logic analyzer to decide when to take a snapshot of the data. This system operates by configuring the logic analyzer to change its criterion for recording data when an instruction in the computer program is executed that communicates with the logic analyzer. The system additionally provides special programming language instructions, which communicate with the logic analyzer. By inserting the special instructions into a computer program, a programmer can select the criterion that the logic analyzer uses to gather data at key points in a computer program. This allows the programmer to specify how data is to be collected by the logic analyzer in different sections of code.

Abstract: A method and apparatus improve the thermal interface between a heat sink and a semiconductor. A support member is attached to a bias plate to facilitate a fixed connection with a surface. The bias plate has a beam for alignment with a heat sink that is attached to the semiconductor. The bias plate is attached to the support member such that the support member forces the beam against the heat sink to improve the thermal interface between the heat sink and the semiconductor. In the method, a heat sink is attached to a semiconductor, and a pivoting beam is biased against the heat sink such that the thermal interface with the semiconductor is improved.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: For a circuit board populated with numerous components having different heights, the need for numerous individual heatsinks to accommodate the circuit board's multilevel surface is eliminated. Instead, heat is transferred to a single integral heatsink via a thermal-conductive material (i.e., a thermal phase change material and/or a resilient gap filling material). A fastener secures the thermal-conductive material between the bottom portion of the heatsink and the multilevel surface, and compresses the thermal-conductive material therein, creating a thermal path sufficient to transfer heat from the multilevel surface to the heatsink so that the circuit board operates within specified design parameters.

Abstract: Heat sinks and methods particularly suited for use on packaged integrated circuits which are not amenable to the use of snap-on heat sinks and on which cemented-on heat sinks prevent conventional probing or reworking of the integrated circuit in the event trouble-shooting of the circuit is required after mounting of the heat sink. In accordance with the invention, a scalable post, based on heat sink size, mass and integrated circuit size, is cemented to the integrated circuit package in a configuration and location not interfering with the later probing or reworking of the integrated circuit, and without interfering with the printed circuit board layout. The post is then used to removably and independently hold a heat sink onto the integrated circuit so that good heat transfer between the integrated circuit and the heat sink is achieved, but still allowing the removal of the heat sink at any time if probing of the integrated circuit is later required. Alternate embodiments are disclosed.

Abstract: A method and apparatus for sharing resources in a network environment. Typically, a computer linked to the Internet may have resources or may provide services, that are usable by other computers. A user, using one or more embodiments of the invention, can access those resources or services as if they were locally situated. An application running on a client can access a resource on a remote computer by submitting a request via an Internet browser. The request is analyzed, converted to proper format and is transferred over the network lines to a server that can satisfy the request. For security reasons, an application may not be authorized to submit a request directly to a server on the Internet. For example, limitations have been implemented that prohibit a requesting application from obtaining access to resources of a server computer unless that application is a trusted application. If a requesting application has a trusted status, then its request for connecting to the server is granted.

Abstract: Methods and apparatus which enable threads to lock and to unlock objects disclosed. According to one aspect of the present invention, a method for associating an object with a first thread includes obtaining the contents of the object header field of the object. The contents obtained from the object header field are then stored into a first location within a stack which is associated with the first thread. A reference indicator, which identifies the stack in which the contents obtained from the object header field are stored, is then stored in the object header field. In one embodiment, the method further includes updating a status indicator associated with the object to essentially show that the reference indicator is stored in the object header field. In such an embodiment, the contents of the object header may include a header value, and the status indicator may be updated to indicate that the object is accessible to the first thread.

Abstract: A method and apparatus that ensures that requests for pages in a particular domain name are routed to the same proxy server by all of a plurality of clients. If, for example, a proxy server has a persistent connection to a server for a domain, all incoming requests for that domain will be sent to the proxy server and will, thus, be able to take advantage of the persistent connection. Each client contains a proxy table that is periodically updated by one or more of the proxy servers. A proxy table in a client contains an entry corresponding to each proxy server. When a client needs to access a resource through a proxy server, the client truncates the address (e.g., the URL) of the resource. Thus, for example, all addresses in a particular domain name are truncated to the same value. The truncated address is then used to hash into the proxy table in the client and to identify a proxy server. The client sends its request to the identified proxy server.

Abstract: A cache memory system having a cache and a cache tag. A cache tag cache is provided to store a subset of the most recently or frequently used cache tags. The cache tag cache is accessed during tag inquires in a manner similar to conventional cache tag inquires. Hits in the cache tag cache have a lower access latency than the tag lookups that miss and require access to the cache tag.

Abstract: A method for causing two programmable interrupts to take place is described herein, using a counter having an output having an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising loading the first register with a first value, loading the second register with a second value, simultaneously causing the counter to count down from said first value to zero, and causing an output of a timer to be a binary “0” during a first portion of the counter period, comparing the value of the first register to the value of the second register, causing, when the value of the first register and the second register are equal, the output of the counter to be a binary “1” until the value of the first register becomes zero.