Abstract: A method and corresponding controller apparatus for creating, updating and maintaining mapping information in a virtual mass storage subsystem. A request to manipulate a virtual block or cluster identifies a particular virtual block number. The virtual block number is mapped to a first physical block number by a direct calculation. A header data structure contained in the first physical block contains mapping information to locate other physical blocks associated with the virtual cluster. In addition to the header data structure, the first physical block contains a portion of the stored data for the corresponding virtual cluster. Additional physical blocks which stored the data of the virtual cluster are located from the mapping information in the header of the first physical block. The methods of the present invention provide improved performance and reduced buffer memory requirements in the virtual mass storage controller circuits of the subsystem as compared to prior approaches.

Abstract: A method and apparatus for aligning a first coordinate system of a digitizing panel with a second coordinate system of a display device. The method includes the steps of displaying a plurality of reference points on the display device, each of the reference points having a X.sub.ref, Y.sub.ref coordinate value, determining a plurality of first Xr, Yr coordinate values from the digitizing panel which are indicative of a plurality of positions of an object positioned relative to the plurality of reference points, determining a plurality of channel gain correction values from the plurality of first Xr, Yr coordinate, values and the plurality of X.sub.ref, Y.sub.ref coordinate values, and storing the plurality of channel gain correction values for use in correcting a second Xr, Yr coordinate value which is indicative of a position of an object relative to the digitizing panel.

Abstract: Methods and associated data structures operable in a RAID subsystem to improve I/O performance. A two level cache data structure and associated methods are implemented with a RAID controller. The lower level cache comprises buffers holding recently utilized blocks of the disk devices. The upper level cache records which blocks are present in the lower level cache for each stripe in the RAID level 5 configuration. The upper level cache serves to reduce the overhead processing required of the RAID controller to determine which blocks are present in the lower level cache. Having more rapid access to this information by lowering the processing overhead enables the present invention to rapidly select between different write techniques to post data and error blocks from low level cache to the disk array. A RMW write technique is used to post data and error checking blocks to disk when insufficient information reside in the lower level cache.

Abstract: A method and apparatus for a method for measuring performance of an I/O bus. The method includes the steps of (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a). One embodiment of the apparatus includes a mechanism for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter. Another embodiment of the apparatus includes a mechanism for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter.

Abstract: A bias current generator includes a first circuit component having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to the first circuit component and the second component, the impedance element (1) having an impedance which increases as an operating temperature of the impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current.

Abstract: A ventilation unit for operative arrangement within an electronic apparatus, the unit including an exterior side having a first exhaust port separated from a second exhaust port, an adjacent interior side having first and second incoming passageways, and a first and second powered air mover; one powered air mover can be located closer to the exterior side than the other air mover. The first powered air mover can be in communication with the first incoming passageway and the first exhaust port, and separated from the second powered air mover by use of a baffle extending generally from the exterior side around and between the two air movers. Additional powered air movers can be accommodated.

Abstract: A method and apparatus for detecting the presence of a stylus relative to an active area of a display screen. The method includes the steps of providing a number of sensors which are positioned to define a boundary surrounding an active area of the display screen, and transmitting an electromagnetic signal from the stylus to the sensors wherein the signal is indicative of the presence of the stylus relative to the active area.

Abstract: Methods and associated apparatus operable in a RAID subsystem having redundant disk array controllers to assure dual, redundant cache consistency while permitting operation of the RAID subsystem in response to host computer I/O requests. The methods and apparatus of the present invention provide for a process of initializing the redundant disk array controllers in response to a power-on reset cycle (or other similar reset cycles). The first controller partially initializes for processing of host requests then awaits the partial initialization of the second controller. After a brief timeout awaiting the second controller, or in response to an erroneous initialization of the second controller, the first controller configures itself to perform host computer I/O requests in a write-through mode (bypassing cache operations) until the second controller eventually initializes. Once both controller are initialized, the redundant caches are synchronized.

Abstract: A method and associated apparatus for automating the filtration and generation of information in a packetized communication system. A filtration table includes entries used in recognizing a valid packet received at a node in a communication system. A mask field in each entry is applied to appropriate fields in the packet (e.g. the ordered set as applied to Fibre Channel communication systems) to determine the validity of the packet with regard to the receiving node. Rules in a field of each entry further qualify the recognition of a received packet (e.g. ordered set) by testing the reception of the packet against other logical rules. Action fields in each record permit definition of actions to be invoked automatically (e.g. automatic adjustment of fill transmissions in Fibre Channel applications) in response to receipt and recognition of a particular packet. The set of packets recognized by the receiving node may be modified by adding, deleting, or modifying the entries in the filtration table.

Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.

Abstract: A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Abstract: A method and architecture for a graphics controller chip. The graphics controller has a display memory for storing video and graphics data. It also has a logic controller, connected to the memory, for performing logic operations on data stored in the memory. Video and graphics data is made available to the graphics controller at a single access port. The graphics controller also has an address range detector for checking the address of the data provided to the port and for disabling logical operations of the logic controller when the address indicates the presence of video data. The video data is thereafter transferred to the display memory on a priority basis.

Abstract: An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter.

Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Abstract: Method for implementing a stripe write operation in a RAID device having XOR command set enabled disk drives on a common interface bus. The method of the present invention improves upon prior designs which do not use the XOR command set by eliminating the need for the RAID controller to include XOR (parity) generation computational elements. Further, the method of the present invention improves upon the stripe write method suggested by the XOR command set specifications in which a stripe is performed by a series of xdwrite XOR command operations issued to the data drives of the RAID array. Rather, the method of the present invention performs parallel standard writes of the data portions of the stripe write, then issues a rebuild XOR command to the parity disk drive to rapidly regenerate the parity blocks in the stripe just written. The method of the present invention reduces the worst case rotational latency delay of the stripe write operation to two rotational latency periods.

Abstract: A pad is adjacent a hole that will be located on the trailing edge of the board when the board is processed through wave soldering. The pad includes a curved side that faces the hole. In addition, corners are absent from the pad. The intersections of sides of the pad occurs as a curve or radiused corner, rather than a verticed corner. Wave soldering the printed circuit board with the pad greatly reduces bridging of a lead inserted into the hole adjacent the pad.

Abstract: A circuit for charging a battery comprising a charging source, a transistor and a charge control device for switching the transistor. When saturated and switched on, the transistor permits flow of charge to the battery from the charging source. The charge control device senses when main power is lost and switches the transistor off to prevent discharge of the battery through the charging source. After the battery is charged the transistor provides a path of least resistance to bleed off unwanted charge from other sources thereby preventing overcharging of the battery. The circuit therefore charges a battery rapidly and prevents overcharging of the battery. The charge control device is operable from a constant supply voltage supplied by a main power source when available or from the charged battery to continue operation despite loss of main power.

Abstract: A method for transferring data in a controller is disclosed which includes the steps of providing a processor having an internal first bus, providing a second bus, connecting a memory device to the second bus, connecting a disk drive to the second bus, transferring first data between the memory device and the processor across the first and second buses, and transferring second data between the memory device and the disk drive across the second bus. A disk array controller architecture is also disclosed.

Abstract: A method for transferring data in a controller having a processor and a controller support device, with the controller connected to a host device and a disk drive. The method includes the steps of providing the controller with a first bus and a second bus, connecting a first bus between the disk drive and the host device, connecting a second bus between the processor and the controller support device, transferring first data between the disk drive and the host device across the first bus, and transferring second data between the processor and the controller support device across the second bus without consuming any portion of the bandwidth of the first bus. A controller architecture is also disclosed.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.