Abstract: A circuit for charging a battery comprising a charging source, a transistor and a charge control device for switching the transistor. When saturated and switched on, the transistor permits flow of charge to the battery from the charging source. The charge control device senses when main power is lost and switches the transistor off to prevent discharge of the battery through the charging source. After the battery is charged the transistor provides a path of least resistance to bleed off unwanted charge from other sources thereby preventing overcharging of the battery. The circuit therefore charges a battery rapidly and prevents overcharging of the battery. The charge control device is operable from a constant supply voltage supplied by a main power source when available or from the charged battery to continue operation despite loss of main power.

Abstract: A method for transferring data in a controller is disclosed which includes the steps of providing a processor having an internal first bus, providing a second bus, connecting a memory device to the second bus, connecting a disk drive to the second bus, transferring first data between the memory device and the processor across the first and second buses, and transferring second data between the memory device and the disk drive across the second bus. A disk array controller architecture is also disclosed.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

Abstract: A method for transferring data in a controller having a processor and a controller support device, with the controller connected to a host device and a disk drive. The method includes the steps of providing the controller with a first bus and a second bus, connecting a first bus between the disk drive and the host device, connecting a second bus between the processor and the controller support device, transferring first data between the disk drive and the host device across the first bus, and transferring second data between the processor and the controller support device across the second bus without consuming any portion of the bandwidth of the first bus. A controller architecture is also disclosed.

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A method and apparatus for storing data on a storage device in which the storage device has a plurality of different zones. Each zone in the storage device has a different transfer rate. The present invention places a video having the highest demand in a zone having the greatest transfer rate, wherein the data transfer of data for that video is maximized.

Abstract: A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control.

Abstract: The invention concerns an adaptive driver circuit which can source and sink current when powered by different power supply voltages. The invention maintains the output voltage substantially constant, for a given load, when the voltage of the power supply changes.

Abstract: A CMOS voltage level shifter that is comprised of a pull-up device coupled between a first voltage supply and an node to pull up that node to the voltage of the first voltage supply. The pull-up device is responsive to a first voltage signal. A pull-down device is also included that is coupled between the node and a reference voltage supply to pull down that node to a voltage of the reference voltage. The pull-down device is responsive to second and third voltage signals. A feedback circuit is included that provides the second voltage signal to the pull-down device. A level shifted output voltage signal is provided at the node.

Abstract: A method and apparatus for pseudo aligned transfers to memory for processors, peripherals and memories. Alignment logic, typically coupled to a peripheral, receives a plurality of data bytes from a processor. The alignment logic uses a control header transferred with the data bytes to determine whether the data bytes require re-alignment. To effect re-alignment, the alignment logic combines, rotates, and masks the data bytes as indicated by the control header.

Abstract: The invention concerns fabrication of oxide-filled isolation trenches in integrated circuits. The invention etches a network of trenches in the surface of a uniformly doped wafer which has experienced no substantial processing steps. Such a wafer will have little, if any, surface damage. Such a wafer will etch to the same depth everywhere, because two major factors which affect etching rate are (a) surface damage and (b) doping non-uniformity, and these factors are absent. The trenches are then filled with oxide. They define islands upon which devices (such as transistors) may now be fabricated.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

Abstract: A high-frequency phase locked loop circuit effectively increases the maximum frequency associated with the CMOS technology. The circuit includes a first phase-locked loop sub-circuit having an input and an output, a second phase-locked loop sub-circuit having an input coupled to the input of the first phase-locked loop circuit and an output, and an exclusive-OR circuit having first and second inputs coupled to the outputs of the first and second phase-locked loop sub-circuits and an output. The first and second phase-locked loop may be arranged in parallel or in a master/slave relationship.

Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

Abstract: A power interface adapter that provides device power connections in a universal burn-in board system. The power interface adapter is a low-cost printed circuit board which interfaces on a one-to-one basis with each burn-in board device socket, thus providing a complete power interface connection. The power interface adapter offers a significant improvement over the present universal burn-in board power connection methods by eliminating device power related manufacturing limitations presently placed on universal burn-in board designs.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU.

Abstract: The invention concerns storage of correction tables for digitizing tablets. A digitizing tablet produces data indicative of position of a stylus. The data does not, in general, exactly indicate the position; errors exist. For example, a tablet may produce a data pair indicating a Cartesian position of (5.0, 6.0) when the position is actually (4.9, 6.1). Correction tables are used to correct the errors. These tables may be viewed as containing correct data for each possible pair of data produced by the tablet. Thus, in this example, a user would (a) receive (5.0, 6.0) from the tablet, (b) look up this data in the table, and (c) find that the actual position which corresponds to this data is (4.9, 6.1). The invention concerns compression of such tables, to reduce storage space.

Abstract: There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.