Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: The invention concerns a stylus for producing a high-voltage, sinusoidal signal for an electrostatic digitizing pad. The high voltage is obtained by applying a sine wave to one lead of the primary of a transformer, and applying the inverse of the sine wave to the other lead of the primary. The secondary of the transformer produces the high voltage, which is developed into a signal which is applied to the digitizing pad.

Abstract: Methods and apparatus for moving pinned data corresponding to a temporarily dead RAID device between the cache memory of a RAID subsystem and a log area. In response to detection of a dead RAID device within a RAID subsystem, the methods of the present invention move any pinned data from the cache memory of the RAID controller to a log area preferably allocated on the disk space of one or more operational RAID devices within the subsystem. In response to revival of the dead RAID device methods of the present invention restore the logged, pinned data from the log area of the operational RAID device(s) to the cache memory as dirty data ready for posting to the revived RAID device. The log area may be either permanently allocated within the RAID subsystem, or may be dynamically allocated in response to recognition of the dead RAID device and freed in response to revival of the RAID device.

Abstract: A bias current generator includes a first circuit component having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to the first circuit component and the second component, the impedance element (1) having an impedance which increases as an operating temperature of the impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current.

Abstract: A method and apparatus for aligning a first coordinate system of a digitizing panel with a second coordinate system of a display device. The method includes the steps of displaying a plurality of reference points on the display device, each of the reference points having a X.sub.ref, Y.sub.ref coordinate value, determining a plurality of first Xr, Yr coordinate values from the digitizing panel which are indicative of a plurality of positions of an object positioned relative to the plurality of reference points, determining a plurality of channel gain correction values from the plurality of first Xr, Yr coordinate, values and the plurality of X.sub.ref, Y.sub.ref coordinate values, and storing the plurality of channel gain correction values for use in correcting a second Xr, Yr coordinate value which is indicative of a position of an object relative to the digitizing panel.

Abstract: A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.

Abstract: A method and architecture for a graphics controller chip. The graphics controller has a display memory for storing video and graphics data. It also has a logic controller, connected to the memory, for performing logic operations on data stored in the memory. Video and graphics data is made available to the graphics controller at a single access port. The graphics controller also has an address range detector for checking the address of the data provided to the port and for disabling logical operations of the logic controller when the address indicates the presence of video data. The video data is thereafter transferred to the display memory on a priority basis.

Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Abstract: An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter.

Abstract: Method for implementing a stripe write operation in a RAID device having XOR command set enabled disk drives on a common interface bus. The method of the present invention improves upon prior designs which do not use the XOR command set by eliminating the need for the RAID controller to include XOR (parity) generation computational elements. Further, the method of the present invention improves upon the stripe write method suggested by the XOR command set specifications in which a stripe is performed by a series of xdwrite XOR command operations issued to the data drives of the RAID array. Rather, the method of the present invention performs parallel standard writes of the data portions of the stripe write, then issues a rebuild XOR command to the parity disk drive to rapidly regenerate the parity blocks in the stripe just written. The method of the present invention reduces the worst case rotational latency delay of the stripe write operation to two rotational latency periods.

Abstract: A pad is adjacent a hole that will be located on the trailing edge of the board when the board is processed through wave soldering. The pad includes a curved side that faces the hole. In addition, corners are absent from the pad. The intersections of sides of the pad occurs as a curve or radiused corner, rather than a verticed corner. Wave soldering the printed circuit board with the pad greatly reduces bridging of a lead inserted into the hole adjacent the pad.

Abstract: A circuit for charging a battery comprising a charging source, a transistor and a charge control device for switching the transistor. When saturated and switched on, the transistor permits flow of charge to the battery from the charging source. The charge control device senses when main power is lost and switches the transistor off to prevent discharge of the battery through the charging source. After the battery is charged the transistor provides a path of least resistance to bleed off unwanted charge from other sources thereby preventing overcharging of the battery. The circuit therefore charges a battery rapidly and prevents overcharging of the battery. The charge control device is operable from a constant supply voltage supplied by a main power source when available or from the charged battery to continue operation despite loss of main power.

Abstract: A method for transferring data in a controller is disclosed which includes the steps of providing a processor having an internal first bus, providing a second bus, connecting a memory device to the second bus, connecting a disk drive to the second bus, transferring first data between the memory device and the processor across the first and second buses, and transferring second data between the memory device and the disk drive across the second bus. A disk array controller architecture is also disclosed.

Abstract: A method for transferring data in a controller having a processor and a controller support device, with the controller connected to a host device and a disk drive. The method includes the steps of providing the controller with a first bus and a second bus, connecting a first bus between the disk drive and the host device, connecting a second bus between the processor and the controller support device, transferring first data between the disk drive and the host device across the first bus, and transferring second data between the processor and the controller support device across the second bus without consuming any portion of the bandwidth of the first bus. A controller architecture is also disclosed.

Abstract: A method of planarizing a non-planar substrate, such as filling vias and contact holes, spreads a suspension of a conducting material suspended in a liquid on a substrate. The suspension includes an organometallic material, preferably with particles of a polymerized tin or indium alkoxide. The material is spread by spinning the substrate after applying the suspension. The carrier liquid and organic groups are removed by baking and curing at elevated temperatures, thereby depositing the conductive material on the substrate in a layer which is more planar than the substrate and which has regions of greater and lesser thickness. A relatively brief etch step removes conductive material from regions of lesser thickness, leaving material filling vias or contact holes.

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A method and apparatus for storing data on a storage device in which the storage device has a plurality of different zones. Each zone in the storage device has a different transfer rate. The present invention places a video having the highest demand in a zone having the greatest transfer rate, wherein the data transfer of data for that video is maximized.

Abstract: A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control.

Abstract: The invention concerns an adaptive driver circuit which can source and sink current when powered by different power supply voltages. The invention maintains the output voltage substantially constant, for a given load, when the voltage of the power supply changes.