Abstract: A directional antenna connected to a portable communications transceiver is adaptively directed towards a remote station in a communication system. The amount of RF power required by the portable device is significantly reduced, relative to a non-directional antenna. The operational period of the transceiver between battery recharges is therefore considerably maximized.

Abstract: An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V.sub.DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract: The invention concerns battery back-up for electronic equipment. A sensor detects a drop in power supply voltage and, in response, connects the back-up battery to the equipment, via a Field-Effect Transistor (FET). The FET causes a lower voltage drop between the battery and the equipment, as compared with a commonly used alternative, namely, a diode.

Abstract: The invention concerns pen-based computers, wherein a pen, or stylus, is positioned on a display of the computer, and produces a signal which allows the computer to detect the position of the stylus. The stylus produces a second signal, which is used as a carrier for telemetry, to transmit data from the stylus to the computer.

Abstract: A CMOS disk drive motor control circuit which has back-EMF regulator circuitry which prevents the back-EMF from the disk drive motor from exceeding a predetermined level. The back-EMF provides an alternate power source for parking the read/write head when power is removed from the disk drive. The circuit is fabricated as a single CMOS integrated circuit which is coupled between a power supply and the disk drive motor. The disk drive control circuit also includes a blocking diode through which power from the power supply flows to the motor and which prevents dissipation of a back-EMF from the motor when power is removed from the motor, and disk drive head parking circuitry which uses the back-EMF to retract and park the disk drive head.

Abstract: A digital data separator is provided for separating clock information and data from a data stream which is subject to varying amounts of undesired jitter which tend to corrupt the data. A read data window of controlled duration is generated for sampling the input data. The current best estimate of the duration of the read data window is stored in a period register as a period register value. The period register value minus one is loaded into a time register as the time register value. A count down cycle is performed by subtracting a value of one from the time register value in each clock cycle during the course of the count down cycle. The read data window is toggled to begin a new read data window when the time register value is near zero, the value remaining in the time register being designated the remaining value.

Abstract: A scalable software architecture, for optimal performance on a RAID level 1, 3, 4 and 5 disk array or tape array. The software architecture consists of a software device driver and one or more driver daemon processes to control I/O requests to the arrays. Implemented in a UNIX or NetWare operating environment, this architecture provides a transparent interface to the kernels I/O subsystem, physical device drivers and system applications. The array driver and I/O daemon can be run on a uni-processor or multi-processor system platform to optimize job control, error recovery, data recreation, parity generation and asynchronous writes.

Abstract: A transfer memory backup system for a RAID level 5 disk array storage system which includes a transfer buffer, wherein write data received by the array is written into a transfer buffer, and a write complete status signal generated, prior to the write data being written to the disk drives within the array. The transfer memory backup system includes a low power, industry standard PCMCIA (Personal Computer Memory Card International Association) device along with a small, temporary voltage source made up of a small rechargeable battery or a high capacitance gold capacitor. Upon the detection of a disk array storage system failure, low power logic provides continuous refresh for the transfer buffer as well as power to the components included in the transfer memory backup system upon a disk array storage system failure. A low power CMOS microprocessor with self contained microcode (mask programmable ROM) controls the transfer of data from the transfer buffer to removable storage medium within the PCMCIA device.

Abstract: A method and apparatus for transferring data between two relatively asynchronous devices and yet matching the maximum data rate of each. Both an asynchronous FIFO and a synchronous FIFO are used to match the data rate of a high speed asynchronous device, such as a SCSI/SCSI2 controller, to a high speed synchronous device, such as a DMA controller. A high speed synchronizer controls both FIFOs such that the asynchronous and the synchronous devices can each run at its maximum data transfer rate during operation.

Abstract: A method of insuring recovery of a quantity write request data in a storage device having a plurality of controllers includes the steps of (1) providing a primary controller for storing the write request data received from a host device, (2) providing an alternate controller having a memory area allocated for use by the primary controller, (3) maintaining a first control block in the primary controller for indicating status of the write request data stored in the primary controller, and (4) maintaining a second control block in the alternate controller for indicating status of the write request data stored in the primary controller.

Abstract: A multi-clock controller circuit includes first and second inputs to which two different types of clocks, such as a crystal oscillator clock and a TTL clock, can be applied. The circuit automatically senses which of the two input clock signals is active and provides that clock signal to an output of the circuit. Power up and power down conditions are achieved without generating non-standard clock pulses on the output through use of a synchronizer stage comprising a plurality of flip flops which determines the number of input clock cycles which are received by the circuit before output clock signals for power up or power down conditions commence.

Abstract: A device and method for processing a plurality of asynchronous interrupt signals provided to respective primary registers. The first provided of the signals is stored in a primary register. The primary registers are then closed to subsequently provided signals. Notice is provided of receipt of the first signal, and the primary registers are read to identify the first signal. Interrupt signals received after the primary registers are closed are stored in secondary registers.

Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.

Abstract: A system and method for testing the functionality of a VGA card and associated monitor. A testing and set up tool or Program is installed in a computer having an operating system. The Program provides a list of modes and timings for a plurality of monitors including the monitor being tested as part of the computer. A user of the Program selects various modes and timings to be tried. Looking at the screen of the monitor enables the user to determine which combinations of modes and timings, for example, are successful. A list is maintained for the modes and timings that prove successful or compatible. The list for compatible combinations is passed to the driver associated with the operating system of the computer. In a DOS environment, for example, the list of compatible combinations is used by the Program to write a Command Line that is used for setting up the associated CONFIG.SYS.

Abstract: A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Abstract: An improved CMOS driver circuit for driving a fast, single-ended, wired-or bus architecture. The driver circuit provides a user-selectable active deassertion assist feature which assists a passive terminator circuit in quickly pulling-up a data or control bus line. The resulting driver circuit provides greater noise immunity to negative voltage transients that result from impedance mismatches caused by poor cable design configurations.

Abstract: A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being processed. A structure such as a closed loop or segment of a spiral may be formed on the surface of the monitor element, and acts as a secondary coil when brought into operative relation with a transformer structure which includes a primary coil, a current source and a sensing device. The sensing device senses variations in the electrical characteristics in the primary coil, caused by the presence of the monitor element, and can thereby determine the temperature or other desired data relating to the monitor element, which is substantially the same as comparable data for the objects being processed.

Abstract: Cancellation of electrostatic noise in digitizing tablet having a shield supplying a signal proportional to the electrostatic noise which is subtracted from the information signal derived from a digitizing grid. A conductive transparent shield is interposed between a digitizing grid and image source so that the same electro-static noise on both. The shield may be grounded on zero to n-1 edges, n being the number of edges of the shield. An electrical signal is taken from an ungrounded side and supplied as an input signal to a difference amplifier, the other input signal being the information signal from the digitizing grid. The output signal from the amplifier is the information signal with the noise signal component cancelled.

Abstract: An architecture for on-line reconfiguration on a RAID level 0, 1, 2, 3, 4 or 5 disk array. This architecture allows the computer system to perform reconfiguration of the disk array transparently, with disk I/O operations being performed concurrently with reconfiguration operations. The reconfiguration process allocates computer system resources necessary to support both the old and new array configurations during the reconfiguration process. Logical areas within the array are sequentially reconfigured from the old configuration to the new configuration. Data in each logical area is read from the area undergoing reconfiguration and thereafter overwritten in accordance with the new array configuration. System I/O requests received during reconfiguration which are directed to unreconfigured areas in the disk array are executed in accordance with the old array configuration.