Abstract: A multi-phase charge sharing technique for electrical and electronic circuits. During a first phase, I/O drivers for circuit outputs that are to change value are deactivated. During a second phase, a plurality of circuit outputs are connected together to allow for charge transfer between higher voltage outputs and lower voltage outputs. Since the output nodes generally have capacitive loads, the common connection of high voltage nodes with low voltage nodes results in charge equilibrium, where the voltage on each commonly connected node acquires the same voltage. As existing charge from high voltage nodes is being used to charge lower voltage nodes, the lower voltage nodes are partially charged without requiring additional external power. Following this charge transfer, the outputs are disconnected from one another and operated in their normal fashion.

Abstract: An AC-DC voltage conversion integrate circuit that integrates all the control and protection circuits, as well as the power transistors, into a single module. Passive components, such as the transformer and capacitors, are very small, as the switching frequency is in the KHz or MHz range. Including one or more integrated switched mode power supply ICs in every wall outlet allows for providing a plurality of DC voltages from such outlets.

Abstract: A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ring oscillator. The VCO transfer characteristic is linearized by piece-wise linear current control added to the delay cell. Additionally, a VCO capable of multi-range operation is provided. With the addition of multiple current sources which control booster inverter current, and by selectively enabling the additional current sources, a VCO with multiple frequency ranges can be achieved.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

Abstract: A data storage system comprising a matrix of intelligent storage nodes interconnected to communicate with each other via a network of busses. The network of busses includes a plurality of first busses for conducting data from and to a corresponding plurality of host system processors and a plurality of second busses, each one of the second busses intersecting with each one of the first busses. The nodes are located at each intersection. The storage nodes each include a data storage device, such as a magnetic disk drive unit, a processor and buffer memory, whereby the node processor controls the storage and retrieval of data at the node as well as being capable of coordinating the storage and retrieval of data at other nodes within the network.

Abstract: A process for coating a surface of a substrate with a polymer material. The process includes heating a polymer to a preselected temperature such that the polymer, if solid, is in a liquid state or if liquid in a less viscous state to form a polymer solution. The polymer solution may contain other components such as a carrier in addition to the polymer. The polymer solution is heated to a preselected temperature below the flashpoint temperature of the polymer solution. The polymer solution is held in reservoir and propelled through a nozzle to create a continuous flow of polymer solution in the form of a stationary wave. The polymer solution flowing out of the nozzle returns to the reservoir, wherein it again will be sent through the nozzle. A substrate having a lower surface is moved over the stationary wave at a preselected rate such that the lower surface of the substrate contacts the stationary wave.

Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract: The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains two cascode amplifiers in series. The analog amplifier also includes a differential amplifier. The invertor is contained within the feedback circuit of the differential amplifier.

Abstract: A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.

Abstract: A method for assuring consistency between data and parity in a disk array system following a reset or a power failure condition which interrupts the execution of write I/O operations. The method includes the steps of: examining drive activities to identify unfinished write I/O operations due to an interrupt condition; logging information necessary to identify the unfinished operations and the array redundancy groups associated with the unfinished operations into a non-volatile memory; and checking for log entries in the non-volatile memory during a disk array subsystem initialization or the restoration of power. For each unfinished operation identified in the log, the method further includes the steps of: performing a bit-wise exclusive-OR of corresponding portions of the data stored within the associated redundancy group to calculate parity consistent therewith; and writing the calculated parity to the parity storage areas within the associated redundancy group.

Abstract: There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resistance, the glassy layer formed maintains its integrity in subsequent processing. Also provided is a method for preparing boron-oxide doped, spin-on glass formulations with a high carbon content having a silane adhesion promoter and boron-dopant incorporated therein.

Abstract: In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.

Abstract: The invention concerns Random-Access Memory (RAM). In many types of RAM currently available, the data on the RAM's output lines can change (or, at least, is no longer guaranteed valid) after the address applied to the RAM changes. The invention maintains the validity of the data after such address changes occur. The data is maintained valid until new data is written to the RAM.

Abstract: A CMOS disk drive motor control circuit which has back-EMF blocking circuitry for preventing the back-EMF from being dissipated when power is removed from the disk drive motor. The back-EMF provides an alternate power source for parking the read/write head. The circuit is fabricated as a single CMOS integrated circuit which is coupled between a power supply and the disk drive motor. The circuit also includes disk drive head parking circuitry and voltage regulator circuitry.

Abstract: A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data sheets. In addition, the capacitive loads of the interconnects between stages are estimated. A switching rate for each cell is then calculated using one of two alternative methods. The first method assumes that the patterns of input signals are statistically independent, and thus estimates the switching rate from the structure of the cell and the switching rates of the inputs. The second method uses known information concerning the relative times when the input signals are high or low to determine the switching rate of the cell. Once the switching rate is known, the output frequency for the cell can be determined. The power dissipation for each cell is then calculated by multiplying the output frequency by the capacitive load.

Abstract: A solid-state array scanner with a color filter at each pixel sensor is provided to accomplish color scanning of color images with a set of pixels sensors for each color pixel. In addition, a scaler device is provided for selectively scaling the output pixel signal from each pixel sensor to correct for color filter loss when scanning black/white images. Thus, while a set of pixel signals must be combined for each color pixel in color mode scanning, in mono mode scanning of black/white images, the pixel signal from each pixel signal may be used. An address means selectively addresses each solid-state pixel sensor device in the array for readout of the illumination intensity, or pixel signal, sensed by that device. Each pixel sensor will have a given color filter dependent upon the sensor's location in the array. From the address of the pixel sensor, the scaler value to compensate for the color filter in mono mode can be selected.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: A voltage controlled current source including feedback circuitry which eliminates the need for a current sensing resistor in series with the output voltage controlled current source. The feedback circuit includes circuitry for generating a reference current which is proportional to, but much smaller than, the output current produced by the current source, and current mirror circuitry for generating a sense current which is equivalent to the reference current. The sense current is provided to a current sense resistor, across which a feedback voltage is developed. The voltage controlled current source further includes an amplifier connected to receive an input control voltage and the feedback voltage for generating the output current in response to the input control voltage and the feedback voltage.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates to ensure heat dissipating air or fluid flow between the substrates. Typically, the substrates are multi-chip modules having a plurality of logic and interconnect chips attached at die mounting locations. Preferably, the logic and interconnect chips are attached to the substrate using flip TAB frames. The substrate includes a pattern interconnect for connecting together all of the chips. The logic chip is based on a standard 10K-50K gate array design with 100 micron pad spacing. The interconnect chip uses an interconnect pattern to connect the logic chips. The interconnect chip uses a lead placement identical to the logic chip, so that a single TAB frame can be used for both chips.