Abstract: Electronic design automation modules simulate the behavior of structures and materials at atomic scale with parameters or a configuration that varies across iterative transformations.

Abstract: Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.

Abstract: A network-based testing method and service integrated with a tool that publishes one or more tagged test cases with tags being executable to reproduce a sequence of events for a system under test, SUT, caused by an original test case. The method is performed in a network and is intended for testing software or hardware by first creating an original test case for a system under test, SUT, and performing a sequence of events for the original test case for testing it. The tested case is stored and information of the performed sequence of events is tagged to the tested case. The tagged test case is then sent to a service that publishes tagged test cases. The service publishes the tagged case in a way to be reproduced via the service.

Abstract: A method and apparatus for structure analysis of a circuit design are described. In one exemplary embodiment, a functional specification of a circuit design is received, where the functional specification is defined based on a behavior layer abstraction. In addition, design codes for the circuit design are received, wherein in each design code of the design codes is defined based on the behavior layer abstraction. Furthermore, the design codes are searched, which is performed in the behavior layer abstraction, for one or more of the design codes that satisfy the functional specification. Each of the design codes that satisfy the functional specification is therefore recognized.

Abstract: Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification.

Abstract: A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: A method is provided to prioritize testing of computer program code comprising: determining first test coverages of items within a first source code version for multiple tests; storing in a non-transitory storage device, a first history that indicates the determined first test coverages of the items within the first source code version; identifying occurrences of the items within a second source code version; determining first weights associated with tests, wherein a respective weight associated with a respective test is indicative of a respective number of respective items within the second source code version that are covered by the respective associated test according to the first history; and prioritizing the multiple respective tests based at least in part upon the determined first weights.

Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Abstract: Roughly described, a method is provided to approximate chemical potentials of elements in ternary and quaternary compound semiconductors, for example III-V semiconductors. In embodiments of the present invention, three, four, or more relationships are solved together to find approximated chemical potentials for each group III element and each group V element. The first relationship relates total energy of a defect-free system to the sum, over all of the group III and group V elements, of (a) provisional chemical potential for the respective element, times (b) number of atoms of the respective element within a supercell. The second relationship describes a stoichiometric balance relationship between total atomic density of all group III atoms and total atomic density of all group V atoms. The other relationship or relationships balance mole fraction ratio between group III atoms, or between group V atoms.

Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.

Abstract: A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states.

Abstract: Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values generated by executing the test program code and the design code during a previously executed simulation.

Abstract: A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted critical design rules are arranged in an order that facilitates searching space reduction techniques, and then the DRC process is sequentially repeated on a user's entire layout pattern for each critical design rule in a first group, then searching space reduction is performed to generate a reduced layout pattern, and then DRC process is performed for all remaining critical design rules using the reduced layout pattern.

Abstract: A method for performing parasitic capacitance extraction of an integrated circuit (IC) design includes: defining a Gaussian surface around an origin net of the IC design; partitioning the Gaussian surface into a plurality of regions; performing an initial plurality of random walks from each region using a Monte Carlo field solver; and dynamically allocating an additional plurality of random walks among the plurality of regions, wherein the allocation is based on statistical errors associated with the initial plurality of random walks for each of the regions. Results from the random walks are averaged to estimate parasitic capacitance of the origin net. The method may include performing the random walks for each region in pairs, wherein a first random walk of the pair is selected in accordance with an anti-symmetric probability function, and a second random walk of the pair is antithetic to the first random walk of the pair.

Abstract: A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of the circuit in accordance with an input trace received by the first prototype and the second prototype.

Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.

Abstract: A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library information. A simulation dynamic library referenced by the component dynamic libraries is loaded. One or more interlibrary adapters corresponding to the component dynamic libraries are loaded to provide compatibility between the component dynamic libraries and an application binary interface of the simulation dynamic library. Instances of hardware components are instantiated based on the component instance information, and the instantiated instances of the hardware components are connected to form the simulation.

Abstract: A circuit detects values stored in bit cells of a memory circuit, for example, a memory circuit with single ended sensing. The circuit injects a charge into a bit line coupled to a bit cell to detect the value stored in the bit cell. A level detector detects the voltage level of the bitline as the charge in injected in the bitline. The sensing circuit determines the bit value stored during the charge injection phase. If the bitline voltage reaches above a high threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a first bit value (for example, bit value 1.) If the bitline voltage stays below a low threshold voltage level as the charge in injected in the bitline, the circuit determines that the bit cell stores a second bit value (for example, bit value 0).

Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).