Abstract: An encoding technique for reducing the power of PDM microphones is disclosed. Digital MEMS microphones utilize a modulation technique called Pulse Density Modulation (PDM), where a single data line (PDMDAT) is used to convey the digital information from the microphone source to a receiver. A characteristic of PDM is that a low noise signal will produce the most transitions, a zero signal will produce an alternating bitstream of logic-1s and logic-0s, and low noise bitstreams will be rich in singleton and doubleton 1s/0s. Typically, CMOS drivers transmit the PDM bitstream signal. CMOS drivers consume power primarily when they transition, so a bitstream rich in singletons and doubletons will increase power consumption. Differential encoding with an XNOR function is used as a singleton-suppression encoder, and a differential encoding with an XOR function is used as a doubleton-suppression encoder.

Abstract: A computerized method comprising receiving, by a simulator logic, inputs including: (i) at least one circuit-level characteristic, and (ii) an architectural description of a neural network, modeling, by the simulator logic, execution of the neural network described in the inputs to obtain results representative of what an analog implementation of the neural network would produce, and determining, by the simulator logic, an accuracy of computational analog elements within the analog implementation of the neural network based on the results obtained during modeling of the neural network is described. In some embodiments, the circuit-level characteristic includes thermal or flicker noise, an inaccuracy of weights between nodes within the neural network, or a frequency response variations of an integrated circuit. Additionally, the circuit-level characteristic can be obtained through simulation of an integrated circuit based on technology-specific measurements of the integrated circuit.

Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor is operable as a stand-alone host processor. The neuromorphic co-processor includes an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through the artificial neural network. In such embodiments, the host processor is a keyword identifier processor configured to transmit one or more detected words to the co-processor over the communications interface. The co-processor is configured to transmit recognized words, or other sounds, to the host processor.

Abstract: A data classification engine includes an interface configured to interface with an input source, where the input source includes sequential data points representative of a time-varying input signal and one or more processors adapted to receive a temporal sequence of data points at a time T, where the one or more processors are further adapted to receive a next sequential data point and facilitate discarding an oldest data point of the temporal sequence at a time T+1. The data classification engine further includes a matrix adapted to align, at time T, to successive temporal portions of the temporal sequence to generate a set of successive outputs from the temporal sequence and one or more memory modules adapted to store the set of successive outputs from the temporal sequence.

Abstract: A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising (“Right”) or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption.

Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

Abstract: A voice-based peer-to-peer communication system may be used to detect voice commands from users to provide a wireless communication voice connection that allows the users to directly communicate with each other. The system may include a first computing device of a first user communicatively coupled to a second computing device of a second user over the wireless connection. The system may process the detected voice command having a phrase, contact name, and voice message. The phrase may include a wake, answer, or stop phrase. The contact name may be utilized to determine whether that contact name matches an entry within a predetermined contact list of the first user, where the matched contact name may be associated with the second user. Finally, the system may generate audio data based on the processed voice command that is then transmitted to the second computing device of the second user over the wireless connection.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor can be operable as a stand-alone processor. The neuromorphic co-processor may include an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through an artificial neural network. In such embodiments, the host processor is a pattern identifier processor configured to transmit one or more detected patterns to the co-processor over a communications interface. The co-processor is configured to transmit the recognized patterns to the host processor.

Abstract: A sensor apparatus includes an interface configured to interface and communicate with a network, a sensor unit configured to measure and report an output representative of a motion state for the sensor apparatus, memory and processing circuitry configured to execute operational instructions to receive the output signal from the sensor unit, where the output signal is representative of one of a plurality of motion states for the sensor unit and the output signal includes information sufficient to determine one or more changes to an environment associated with the sensor apparatus. The processing circuitry is configured to classify, via an artificial intelligence model, the output signal according to previously classified events to produce a classified output determine whether to transmit a notification to the network.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a hybrid neural network including a plurality of analog layers, a digital layer, and a plurality of data outputs. The plurality of analog layers is configured to include programmed weights of the neural network for decision making by the neural network. The digital layer, disposed between the plurality of analog layers and the plurality of data outputs, is configured for programming to compensate for weight drifts in the programmed weights of the neural network, thereby maintaining integrity of the decision making by the neural network. Also provided herein is a method including, in some embodiments, programming the weights of the plurality of analog layers; determining the integrity of the decision making by the neural network; and programming the digital layer of the neural network to compensate for the weight drifts in the programmed weights of the neural network.

Abstract: An audio processing circuit includes an audio front end (AFE) configured to generate audio data in response to audio signals received from one or more microphones. One or more special purpose engines (SPEs) are configured to: generate prediction data via a usage model; generate bias adjustment data based on the prediction data; adjust a threshold of an audio event recognition engine based on the prediction data; and determine, via the audio event recognition engine and based on audio data, when an audio event is detected.

Abstract: Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network.

Abstract: Provided herein is a system including, in some embodiments, one or more servers and one or more database servers configured to receive user-specific target information from a client application for training a neural network on a neuromorphic integrated circuit. The one or more database servers are configured to merge the user-specific target information with existing target information to form merged target information in the one or more databases. The system further includes a training set builder and a trainer. The training set builder is configured to build a training set for training a software-based version of the neural network from the merged target information. The trainer is configured to train the software-based version of the neural network with the training set to determine a set of synaptic weights for the neural network on the neuromorphic integrated circuit.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Abstract: Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.