Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Abstract: Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor is operable as a stand-alone host processor. The neuromorphic co-processor includes an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through the artificial neural network. In such embodiments, the host processor is a keyword identifier processor configured to transmit one or more detected words to the co-processor over the communications interface. The co-processor is configured to transmit recognized words, or other sounds, to the host processor.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a host processor, a digitally implemented neural network co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor can be operable as a stand-alone processor. The neural network co-processor may include a digitally implemented neural network. The co-processor is configured to enhance special-purpose processing of the host processor through an artificial neural network. In such embodiments, the host processor is wake keyword identifier processor configured to transmit one or more detected patterns to the co-processor over a communications interface. The co-processor is configured to transmit the recognized patterns to the host processor which can then identify and verify wake keywords spoken by a known user.

Abstract: Provided herein is an integrated circuit for generating augmented training data, including a host processor configured to receive a signal stream. The integrated circuit also has a co-processor commutatively coupled to the host-processor includes a neural network with at least a first set of weights configured to identify one or more target signals from the signal stream received from the host processor. A plurality of augmentation tools are also accessible to the integrated circuit. Finally, the integrated circuit, coupled computing device or other suitable digital signal processor stores a plurality of the one or more identified target signals, and upon reaching a predetermined threshold of identified target signals, utilizes the plurality of augmentation tools to generate an extended set of target signals, and generates a second set of weights for the neural network based on the extended set of target signals generated by the augmentation tools.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor is operable as a stand-alone host processor. The neuromorphic co-processor includes an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through the artificial neural network. In such embodiments, the host processor is a keyword identifier processor configured to transmit one or more detected words to the co-processor over the communications interface. The co-processor is configured to transmit recognized words, or other sounds, to the host processor.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a special-purpose host processor, a neuromorphic co-processor, and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The special-purpose host processor is operable as a stand-alone host processor. The neuromorphic co-processor includes an artificial neural network. The co-processor is configured to enhance special-purpose processing of the host processor through the artificial neural network. In such embodiments, the host processor is a keyword identifier processor configured to transmit one or more detected words to the co-processor over the communications interface. The co-processor is configured to transmit recognized words, or other sounds, to the host processor.

Abstract: Provided herein is a system including, in some embodiments, one or more servers and one or more database servers configured to receive user-specific target information from a client application for training a neural network on a neuromorphic integrated circuit. The one or more database servers are configured to merge the user-specific target information with existing target information to form merged target information in the one or more databases. The system further includes a training set builder and a trainer. The training set builder is configured to build a training set for training a software-based version of the neural network from the merged target information. The trainer is configured to train the software-based version of the neural network with the training set to determine a set of synaptic weights for the neural network on the neuromorphic integrated circuit.

Abstract: A computerized method comprising receiving, by a simulator logic, inputs including: (i) at least one circuit-level characteristic, and (ii) an architectural description of a neural network, modeling, by the simulator logic, execution of the neural network described in the inputs to obtain results representative of what an analog implementation of the neural network would produce, and determining, by the simulator logic, an accuracy of computational analog elements within the analog implementation of the neural network based on the results obtained during modeling of the neural network is described. In some embodiments, the circuit-level characteristic includes thermal or flicker noise, an inaccuracy of weights between nodes within the neural network, or a frequency response variations of an integrated circuit. Additionally, the circuit-level characteristic can be obtained through simulation of an integrated circuit based on technology-specific measurements of the integrated circuit.

Abstract: A method comprising the steps of responding to expiration of a timer, transmitting a signal from the timer to circuitry; responsive to receiving the signal, retrieving by the circuitry (i) first values stored in an analog array, and (ii) second values stored in a digital non-volatile memory; performing, by the circuitry, operations comprising a comparison of the first values and the second values; analyzing, by the circuitry, results of the comparison to determine whether an error is greater than or equal to a predefined threshold; responsive to determining the error is greater than or equal to the predefined threshold, initiating, by the circuitry, operations to reprogram the analog array with the second value is described.

Abstract: Disclosed herein is a neuromorphic integrated circuit, including in many embodiments, a neural network disposed in a multiplier array in a memory sector of the integrated circuit, and a plurality of multipliers of the multiplier array, a multiplier thereof including at least one transistor-based cell configured to store a synaptic weight of the neural network, an input configured to accept digital input pulses for the multiplier, an output configured to provide digital output pulses of the multiplier, and a charge integrator, where the charge integrator is configured to integrate a current associated with an input pulse of the input pulses over an input pulse width thereof, and where the multiplier is configured to provide an output pulse of the output pulses with an output pulse width proportional to the input pulse width.

Abstract: Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof. Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Abstract: Provided herein is an integrated circuit including, in some embodiments, a hybrid neural network including a plurality of analog layers, a digital layer, and a plurality of data outputs. The plurality of analog layers is configured to include programmed weights of the neural network for decision making by the neural network. The digital layer, disposed between the plurality of analog layers and the plurality of data outputs, is configured for programming to compensate for weight drifts in the programmed weights of the neural network, thereby maintaining integrity of the decision making by the neural network. Also provided herein is a method including, in some embodiments, programming the weights of the plurality of analog layers; determining the integrity of the decision making by the neural network; and programming the digital layer of the neural network to compensate for the weight drifts in the programmed weights of the neural network.

Abstract: Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

Abstract: Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network.

Abstract: Disclosed herein is a neuromorphic integrated circuit including, in some embodiments, an erasable memory sector including an analog multiplier array of two-quadrant multipliers, the two-quadrant multipliers including cells configured to accept repeated pulses to set weight values for the cells within a tolerance for the weight values of the cells. Also disclosed herein is a method including, in some embodiments, erasing a memory sector of an integrated circuit including an analog multiplier array of two-quadrant multipliers; applying a first set of programming pulses to cells of the two-quadrant multipliers to set weight values for the cells; determining whether or not the weight values of the cells are within a tolerance for the weight values of the cells; and applying a second set of programming pulses to complement cells of the two-quadrant multipliers to compensate for cells not within the tolerance for the weight values of the cell.