Abstract: A set of methods for discovery of nodes where at least some of the nodes use directional antennas is presented. The methods consist primarily of partitioning the search space into tiers based on elevation angles and adjusting parameters used to construct tiling patterns and slots for discovery messaging, and search methods patterns. The methods further include partitioning into subslots as well as characterization of HAIL slots and rendezvous slots. The HAIL slots and rendezvous slots are allocated within a search schedule and synched across multiple platforms for greater efficiency of communication.

Abstract: Techniques are disclosed for providing retractable control fins on an underwater vehicle. The retractable control fins can be extended away from a main hull portion of the underwater vehicle and retracted inwards to a stowage region within the hull portion to protect the fins from damage and reduce an overall outer diameter (e.g., in the case of a cylindrical body) of the underwater vehicle. In some embodiments, the control fins are folded inwards to reduce the vehicle diameter. In other embodiments, the control fins are pulled inwards using a rotating structure designed to slide the control fins through an opening and into an inner portion of the hull to reduce the vehicle diameter. The retraction of the fins through the various retraction mechanisms reduces the envelope diameter of the underwater vehicle.

Abstract: A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

Abstract: A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.

Abstract: A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input.