Abstract: A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half the current of the memory cell. The reference voltage is then applied to other reference cells in a memory array.

Abstract: A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.

Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to included at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor.

Abstract: A charge pump based voltage regulator with smart power regulation employs an architecture that requires that the charge pump current be a linear combination of the load current and a clamp current with a possible offset current. The smart power regulation is based on automatic load activity (or load current) detection using the clamp current. The clamp current and the filtered charge pump current are compared with one another; and the charge pump current is then adjusted accordingly by stepping the frequency of the clock driving the charge pump, optimizing the power consumption of the entire voltage regulator with varying load activity. The negative voltage regulation is independent of the integrated circuit positive supply voltage. In one embodiment, a derivative of the desired output voltage is compared with a reference voltage to generate a clamp current control signal. In another embodiment, the reference voltage is solely positive.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.

Abstract: A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.

Abstract: A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to include at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.

Abstract: The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.

Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract: A semiconductor device having a thyristor is arranged in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices, as well as facilitates the implementation of the semiconductor device in a variety of applications. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor.

Abstract: A semiconductor device is adapted to inhibit the formation of a parasitic MOS-inversion channel between an emitter region and a gated base in a capacitively-coupled thyristor device. According to an example embodiment of the present invention, a thyristor having first and second base regions coupled between emitter regions is gated, via one of the base regions, to a control port. The control port exhibits a workfunction between the control port and the base region that inhibits the formation of a conductive channel between the base region and an adjacent emitter region, such as when the semiconductor device is in a standby and/or a read mode for memory implementations. The workfunction is selected such that the parasitic MOS-inversion channel would turn on is sufficiently high to enable the operation of the device at voltages that are optimized for a particular implementation while remaining below VT.

Abstract: A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.

Abstract: Parasitic current leakage from a thyristor-based semiconductor device is inhibited. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor body portion and a control port located in a substrate, the control port being adapted for capacitively coupling to the thyristor body portion for controlling current flow therein. The substrate further includes a doped circuit region separated by a channel region from another doped region of similar polarity in the substrate. The control port faces the channel region in the substrate, and the channel region is susceptible to current leakage in response to voltage pulses being applied to the control port for controlling current flow in the thyristor.

Abstract: A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e.g., for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions.

Abstract: A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween.