Abstract: Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.

Abstract: Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.

Abstract: Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) with configurable input/output (I/O) circuits for optimally operating with two or more interfaces. Some embodiments optimally operate over the two or more interfaces by supporting a particular voltage for each interface. Also, some embodiments optimally operate over two or more interfaces by supporting a particular frequency for each supported voltage whereby supporting a particular frequency involves producing sufficient current drive at each voltage to support the particular frequency.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Some embodiments provide an integrated circuit (IC) that has a first interface rate for exchanging signals in at least one direction with a circuit outside of the IC. The IC has multiple reconfigurable circuits. Each of the reconfigurable circuits is for reconfiguring at a second rate. The second rate is faster than the first interface rate. Each of the reconfigurable circuits reconfigures when configuration data that specifies an operation of the particular reconfigurable circuit changes from a first configuration data set that is stored in the IC to a second configuration data set that is also stored in the IC.

Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of the sets are user multiplexers. Each particular user multiplexer has input and output terminals and has a set of select terminals for receiving a set of user-design signals that directs the particular multiplexer to connect a set of the input terminals to a set of the output terminals. The user-design signals are signals generated internally by the IC.

Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Abstract: An integrated circuit (IC) is disclosed that includes a set of configurable logic circuits. Each configurable logic circuit configurably performs a set of functions. A particular configurable circuit receives configuration data defining a function for the particular configurable circuit. In some embodiments, one configuration of a configurable circuit is to add two input signals received by the configurable circuit. Also, in some embodiments, one configuration is to subtract two input signals received by a configurable circuit. In some such embodiments, each configurable logic circuit receives a first input signal, a second input signal, and a carry input signal and generates a propagate and generate signal for the add or subtract operation based on the inputs to the configurable circuit and the configuration of the configurable circuit.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.

Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.

Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.

Abstract: Some embodiments provide an integrated circuit that includes several groups of circuits, each group of circuits includes a set of configurable logic circuits. The integrated circuit has at least one direct connection, without any intervening interconnect circuits, that connects an output of a configurable logic circuit in one group of circuits to another circuit in another group of circuits that does not neighbor the first group of circuits and that is not aligned with the first group of circuits. In some embodiments, the direct connection has intervening buffer circuits, but no other intervening circuits.

Abstract: Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.