Patents Assigned to Taiwan Semiconductor Co., Ltd.
  • Patent number: 9741825
    Abstract: A method for manufacturing a field effect transistor having a widened trench forms sequentially an epitaxial layer, a trench, an oxidation layer, a trench-oxidation layer, a polysilicon layer, a residual oxidation layer, an electrode portion, a lower trench, a widened trench, a gate portion, a body region, a source region, an interlayer dielectric layer and a source electrode. The trench is formed at the epitaxial layer. The oxidation layer, the trench-oxidation layer and a polysilicon layer are then formed. The residual oxidation layer and the electrode portion are formed in the trench by etching the polysilicon layer and the trench-oxidation layer. The lower trench is formed by etching the epitaxial layer. The widened trench is formed by widening a portion of the trench away from a trench bottom so as to have the electrode portion and the residual oxidation layer disposed at the lower trench.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 22, 2017
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Yi-Lung Tsai, Aryadeep Mrinal, Mohammad Amanullah, Po-Wen Yang, Shu-Siang Liang
  • Patent number: 9433045
    Abstract: A drive circuit with an external mode-adjusting pin includes an operational mode control circuit and a drive processing circuit. The operational mode control circuit further includes a current mirror circuit, a resistor, a capacitor and a comparator. The first comparator input port receives a reference voltage. The second comparator input port couples the second output port of the current mirror and the capacitor. The current mirror circuit bases on a resistor current to generate a charge current for charging the capacitor. As the charge voltage at the second comparator input port reaches a reference voltage, a trigger signal is outputted to the drive processing circuit for controlling the switches thereof. The external pin is defined to one end of the resistor or the capacitor for varying the resistance or the capacitance respectively to determine the operational mode for the driven circuit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Yueh-Hua Chiang
  • Patent number: 8779545
    Abstract: A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventors: Chao-Hsin Huang, Chih-Chiang Chuang
  • Patent number: 8736012
    Abstract: A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventors: Chao-Hsin Huang, Chih-Chiang Chuang
  • Publication number: 20130270668
    Abstract: A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown.
    Type: Application
    Filed: January 9, 2013
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: CHAO-HSIN HUANG, CHIH-CHIANG CHUANG
  • Publication number: 20130270669
    Abstract: A semiconductor structure with dispersedly arranged active region trenches is provided. The semiconductor structure comprises a semiconductor substrate, an epitaxial layer, and an active region dielectric layer. The semiconductor substrate is doped with impurities of a first conductive type having a first impurity concentration. The epitaxial layer is doped with impurities of the first conductive type having a second impurity concentration and is formed on the semiconductor substrate. The epitaxial layer has a plurality of active region trenches formed therein being arranged in a dispersed manner. The active region dielectric layer covers a bottom and a sidewall of the active region trenches. Wherein, the active region trench has an opening in a tetragonal shape on a surface of the epitaxial layer, and the first impurity concentration is greater than the second impurity concentration.
    Type: Application
    Filed: January 9, 2013
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Chao-Hsin HUANG, Chih-Chiang CHUANG
  • Patent number: 7258503
    Abstract: A device for adjusting the position of a printer head of a barcode printer includes a casing mounted to the barcode printer and a base movably coupled to the casing. A slide board is slidably supported on the base and carries the printer head. A first adjuster is arranged between the slide board and the base to selectively move and thus adjust the position of the printer head in the longitudinal direction. A second adjuster couples the first adjuster to the base to selectively move the slide board on the base in the transverse direction, which in turn adjusts the transverse position of the printer head. A third adjuster couples the base to the casing to selectively move the base with respect to the casing and thus adjust the position of the printer head in the vertical direction.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: August 21, 2007
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Wen Chin Lu
  • Patent number: 7242559
    Abstract: An I/O circuit is disclosed for tolerating a high voltage input without incurring a leakage current. An ESD current bypass module is coupled between a power supply node and a circuit pad. A high voltage tolerant charge module is used for disabling the ESD current bypass module when the circuit pad receives a high voltage input that is higher than a voltage at the power supply node. In addition, a high voltage tolerant discharge module may be included for alleviating the ESD current bypass module from a voltage overstress when the circuit pad receives a low voltage input that is lower than the voltage at the power supply node.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: July 10, 2007
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chi-Di An
  • Patent number: 7242558
    Abstract: An electrostatic discharge protection (ESD) circuit is disclosed for protecting a pad of an integrated circuit from ESD events. The ESD circuit has an ESD trigger module having a first and second transistors connected in series, between the pad and a first common node, at least one ESD protection module having a third and fourth transistors connected in series between the pad and a second common node, and a current limiting resistor in the ESD trigger module connected between the first and second common nodes, wherein the first and second transistors have a shorter channel length than that of the third and fourth transistors so that the ESD trigger module is turned on before the ESD protection module when an ESD event happens on the pad.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: July 10, 2007
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chung-Hui Chen
  • Patent number: 6874964
    Abstract: A printing module mounted inside the top cover of a barcode printer and adapted to print a barcode on a sheet member is constructed to include an output unit having a relatively higher first mounting face and a relatively lower second mounting face and a USB connector, a bottom panel affixed to the second mounting face of the output unit and hooked on the bottom side of the output unit, a locating plate affixed to the first mounting face of the output unit, a holder frame coupled to the locating plate and adapted to detachably secure the printing module to the inside of the top cover of the barcode printer by a hook joint.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chen Cheng Lee
  • Patent number: 6814126
    Abstract: A sheet member impression structure formed of a rod member and two sheet member impression devices is disclosed in which each sheet member impression device includes a casing slidably mounted on the rod member, an adjustment unit mounted inside the casing and partially extended out of the casing for operation by the user to adjust the position of the casing on the rod member, and a press member supported on the bottom side of a spring member inside the casing and forced by the spring member to press on a pressure board keeping a transferring sheet member smooth.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: November 9, 2004
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chen Cheng Lee
  • Patent number: 5803625
    Abstract: A bar code printing device including a base frame, a cover turned about a pivot in the base frame, torsional springs mounted around the pivot to force the cover outwards from the base frame, gear wheel and sector gear assemblies mounted between the base frame and the cover to buffer the spring force of the torsional springs, a sticker reel mounted in the base frame and turned by a step motor to let off a sticker for printing, a ribbon reel mount fastened to the cover on the outside, a ribbon reel mounted on the ribbon reel mount and turned by a DC motor through a reducing gear to turn a ribbon over the sticker, the ribbon reel having a tension spring adapted for adjusting the diameter of the ribbon reel subject to the size of the ribbon to be used, and a control circuit for controlling the operation of the DC motor and the step motor.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: September 8, 1998
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chih Jung Lee
  • Patent number: D395880
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: July 7, 1998
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chin-Jung Lee
  • Patent number: D396459
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: July 28, 1998
    Assignee: Taiwan Semiconductor Co., Ltd.
    Inventor: Chin-June Lee