Abstract: A light source for EUV is provided. The light source includes a target droplet generator, a laser generator, and a controller. The target droplet generator is configured to provide target droplets to a source vessel. The laser generator is configured to provide first laser pulses according to a control signal to irradiate the target droplets in the source vessel. The controller is configured to provide the control signal according to at least two of process parameters including temperature of the source vessel, droplet positions of the target droplets, and beam sizes and focal points of the first laser pulses. When the average value or the standard deviation of the temperature of the source vessel and the droplet positions of the target droplets exceed the predetermined range, the controller is configured to provide the control signal to the laser generator to stop providing the first laser pulses.

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A semiconductive structure includes a first substrate comprising an interconnection layer and a first conductor protruding from the interconnection layer, a second substrate comprising a second conductor bonded with the first conductor, a first cavity between and sealed by the first substrate and the second substrate and the first cavity has a first cavity pressure, a second cavity between and sealed by the first substrate and the second substrate and the second cavity has a second cavity pressure, a first surface of the interconnection layer is a sidewall of the first cavity, wherein the first cavity pressure is less than the second cavity pressure.

Abstract: Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

Abstract: A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.

Abstract: A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.

Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.

Abstract: In at least one embodiment, a method includes applying an input voltage external to a semiconductor chip to a first circuit of the semiconductor chip to generate an output voltage external to the semiconductor chip. The first circuit is electrically coupled to a resistive device. A logic state of the resistive device is determined based on a logic state of the external output voltage.

Abstract: Exemplary microelectromechanical system (MEMS) devices, and methods for fabricating such are disclosed. An exemplary method includes providing a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes a first silicon layer separated from a second silicon layer by an insulator layer; processing the first silicon layer to form a first structure layer of a MEMS device; bonding the first structure layer to a substrate; and processing the second silicon layer to form a second structure layer of the MEMS device.

Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.

Abstract: An embodiment is a method for de-embedding. The method comprises forming a primary structure in a semiconductor chip and forming an auxiliary structure in the semiconductor chip. The auxiliary structure replicates a first portion of the primary structure. The method further comprises determining a transmission matrix for each of the primary structure and the auxiliary structure based on measurements and extracting a transmission matrix of a first component of the primary structure by determining a product of the transmission matrix of the primary structure and an inverse of the transmission matrix of the auxiliary structure.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: A metal-ceramic multilayer structure is provided. The underlying layers of the metal/ceramic multilayer structure have sloped sidewalls such that cracking of the metal-ceramic multilayer structure may be reduced or eliminated. In an embodiment, a layer immediately underlying the metal-ceramic multilayer has sidewalls sloped less than 75 degrees. Subsequent layers underlying the layer immediately underlying the metal/ceramic layer have sidewalls sloped greater than 75 degrees. In this manner, less stress is applied to the overlying metal/ceramic layer, particularly in the corners, thereby reducing the cracking of the metal-ceramic multilayer. The metal/ceramic multilayer structure includes one or more alternating layers of a metal seed layer and a ceramic layer.

Abstract: A circuit structure is provided. The circuit structure includes a capacitor including a top capacitor electrode; a bottom capacitor electrode parallel to the top capacitor electrode; and an insulating layer between the top and the bottom capacitor electrodes. The insulating layer includes a dielectric rod enclosed by a dielectric material. The dielectric rod has a higher dielectric constant than that of the dielectric material. The circuit structure may be a printed circuit board or packaging substrate, wherein the capacitor is formed between the two layers of the capacitor. Additional dielectric rods may be formed in the insulating layer of the capacitor and spaced apart from the dielectric rods.

Abstract: The present disclosure provide an integrated circuit. The integrated circuit includes a through-silicon-via (TSV) trench configured in a semiconductor substrate; a conductive pad formed on the semiconductor substrate, the conductive pad being adjacent the TSV trench; a silicon nitride layer disposed over the conductive pad and in the TSV trench; a titanium layer disposed on the silicon nitride layer; a titanium nitride layer disposed on the titanium layer; and a copper layer disposed on the titanium nitride layer.

Abstract: In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.

Abstract: In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.