Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

Abstract: An extreme ultraviolet (EUV) photolithography system detects debris travelling from an EUV generation chamber to a scanner. The photolithography system includes a detection light source and a sensor. The detection light source outputs a detection light across a path of travel of debris particles from the EUV generation chamber. The sensor senses debris particles by detecting interaction of the debris particles with the detection light.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: An apparatus includes a first portion and a second portion. The first portion includes a first front side wall, a first rear side wall, a top wall, and at least one pivotal pin structure extending from the first rear side wall. The at least one pivotal pin structure comprises a base, a shaft, and a head having a non-circular cross-sectional shape. The second portion includes a second front side wall, a second rear side wall, a bottom wall, and at least one pin holder extending from the second rear side wall. The at least one pin holder defines an opening for accepting the head of the at least one pivotal pin structure at an alignment. The head of the at least one pivotal pin structure extends through the opening. The first portion and the second portion are pivotally movable between an open configuration and a closed container configuration.

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. An array of sensors sense the extreme ultraviolet radiation and charged particles emitted by the droplets. A control system analyses sensor signals from the sensors and adjusts plasma generation parameters responsive to the sensor signals.

Abstract: Disclosed are apparatus and methods for optical coupling.

Abstract: The present disclosure provides a system and method for providing uninterrupted power to an external device. The system and method include a power supply module coupled to an AC power source and to an external device via a power line, a switching module coupled to the power line, a redundant power supply unit coupled to the AC power source and to the switching module. The switching module is configured to detect an electrical state of the power line and connect the redundant power supply unit to the power line for providing redundant power to the external device based upon the detected electrical state.

Abstract: Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers. A wafer bonding system includes a camera configured to monitor bonding between two semiconductor wafers. Wafer bonding defect detection circuitry receives video data from the camera, and detects a bonding defect based on the received video data.

Abstract: In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region, second channel nanostructures in a second device region, a dielectric fin at a boundary between the first device region and the second device region, a high-k dielectric layer surrounding each of the first channel nanostructures and each of the second channel nanostructures and over the dielectric fin, a first work function layer surrounding each of the first channel nanostructures and over the high-k dielectric layer and a second work function layer surrounding each of the second channel nanostructures and over the high-k dielectric layer and the first work function layer. The first work functional layer fully fills spaces between the first channel nanostructures and has an edge located above the dielectric fin. The second work functional layer fully fills spaces between the second channel nanostructures.

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

Abstract: A semiconductor device includes first transistor having a first gate stack and first source/drain regions on opposing sides of the first gate stack; a second transistor having a second gate stack and second source/drain regions on opposing sides of the second gate stack; and a gate isolation structure separating the first gate stack from the second gate stack. The gate isolation structure includes a dielectric liner having a varied thickness along sidewalls of the first gate stack and the second gate stack and a dielectric fill material over the dielectric liner, wherein the dielectric fill material comprises a seam.

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.