Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.
Abstract: An extreme ultra-violet (EUV) mask and method for fabricating the same is disclosed. For example, the EUV mask includes a substrate, a multi-layered mirror layer formed on the substrate, a metal capping layer formed on the multi-layered mirror layer, and a multi-layered absorber layer formed on the metal capping layer. The multi-layered absorber layer includes features etched into the multi-layered absorber layer to define structures on a semiconductor device.
Abstract: A device comprises a first dielectric layer, a first conductor, a carbon-containing etch stop layer, a second dielectric layer, and a second conductor. The first conductor has a lower portion in the first dielectric layer. The carbon-containing etch stop layer wraps an upper portion of the first conductor. The second dielectric layer is over the carbon-containing etch stop layer. An interface formed by the second dielectric layer and the carbon-containing etch stop layer is higher over the first conductor than over the first dielectric layer. The second conductor is in the second dielectric layer.
Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
Abstract: The present disclosure describes a lithography apparatus comprising a photoresist coating unit configured to perform one or more coating processes on a substrate. The lithography apparatus further comprises a detection unit configured to determine a contamination level of a contaminant from the one or more coating processes adheres on a sidewall of the lithography apparatus. The lithography apparatus further comprises a controller unit configured to adjust one or more operations of the lithography apparatus based on a comparison between the contamination level and a baseline cleanliness requirement of the lithography apparatus.
Abstract: A semiconductor structure including a semiconductor substrate, an interconnect structure disposed over the semiconductor substrate, and a bonding structure disposed over the interconnect structure is provided. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating through the dielectric layer, and a thermal conductive feature penetrating through the dielectric layer. The thermal conductive feature includes a thermal routing and thermal pads, and the thermal pads are disposed on and share the thermal routing.
Abstract: A method for fabricating an image sensor device is provided. The method includes forming a plurality of photosensitive pixels in a substrate; depositing a dielectric layer over the substrate; etching the dielectric layer, resulting in a first trench in the dielectric layer and laterally surrounding the photosensitive pixels; and forming a light blocking structure in the first trench, such that the light blocking structure laterally surrounds the photosensitive pixels.
Abstract: An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.
Abstract: A probe card module including a probe card assembly and a strengthening structure is provided. The probe card assembly includes a first surface, a second surface opposite to the first surface, and a plurality of probes protruding from the first surface. The second surface includes a central zone and a peripheral zone surrounding the central zone. Projections of the probes on the second surface are located at the central zone. The strengthening structure is disposed on the second surface and includes two support bases which protrude from the peripheral zone and are away from each other, and the strengthening structure also includes an arc-shaped reinforcement assembly connected to the two support bases, where the arc-shaped reinforcement assembly protrudes toward and leans against the central zone.
February 18, 2020
July 22, 2021
Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation.
Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.
Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.
Abstract: A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.
Abstract: A package structure includes a package component, a stacked die package, a plurality of optical fibers and a heat spreading structure. The stacked die package is disposed on and electrically connected to the package component. The stacked die package includes a first semiconductor die and a plurality of second semiconductor dies. The first semiconductor die has a plurality of first bonding elements. The second semiconductor dies are disposed on the first semiconductor die and have a plurality of second bonding elements, wherein the plurality of first bonding elements and the plurality of second bonding elements are facing one another and bonded together through hybrid bonding. The plurality of optical fibers is attached to the plurality of second semiconductor dies of the stacked die package. The heat spreading structure is disposed on the package component and surrounding the stacked die package.
Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.
Abstract: A semiconductor device includes a fin structure, a source/drain region, a first inter-layer dielectric (ILD) layer, a first contact plug, and a second contact plug. The fin structure extends above a substrate. The source/drain region is in the fin structure. The first ILD layer is over the source/drain region. The first contact plug extends through the first ILD layer to a silicide region of the source/drain region. The second contact plug is over the first contact plug. The first contact plug has a protruding portion extending above the first ILD layer and laterally surrounding a lower part of the second contact plug.
Abstract: A semiconductor device includes a semiconductor fin and a gate structure above the semiconductor fin. The semiconductor fin includes a bottom portion and a top portion above the bottom portion. The bottom portion and the top portion are made of different materials. The top portion includes a head part and a neck part between the head part and the bottom portion. The neck part has a width less than a width of the head part, and the neck part is in contact with the bottom portion.
Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.
Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.
Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.