Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a patterned dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a patterned capping layer formed upon the patterned dielectric layer. The patterned capping layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 0 to about 200 degrees centigrade and a radio frequency power of from about 100 to about 1000 watts per square centimeter substrate area. The patterned capping layer provides for attenuated abrasive damage to the dielectric layer incident to the damascene method and is typically partially planarized incident to the damascene method.

Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.

Abstract: Detecting blade vibration via ultrasonic waves is disclosed. The blade may be part of a robot that is used in conjunction with semiconductor device fabrication. A process chamber is provided that has a sidewall and a base defining a cavity contained therein. A rotatable blade is mounted at a center of the cavity that has a base portion and a tip portion extensible from the center to the sidewall of the process chamber. One or more ultrasonic sensors are mounted on the base adjacent to the sidewall. Ultrasonic waves are sent and received toward and reflected by the tip portion of the wafer blade to determine the tip portion's position. In this way, vibrational movement of the blade can be detected.

Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

Abstract: A threadless docking fixture for removably mounting a test device in functional electrical engagement with a test head on a parametric semiconductor wafer testing system. The threadless docking fixture comprises a housing in which is mounted the test device. The housing is fitted with a pivoting lock handle which terminates in a pair of lock plates rotatably attached to opposite sides of the housing. An arcuate lock flange on each lock plate us removably engages a lock rod which extends from a corresponding one of a pair of anchor plates which are mounted on the test head of the wafer testing system. Accordingly, each lock flange engages the corresponding lock rod and the test device is mounted in functional electrical engagement with the test head as the handle is pivoted from an unlock to a lock position.

Abstract: A device for controlling emission of electrons from an arc chamber of a plasma flood system into an ion beam in an ion implanter for implanting ions into a substrate. In one embodiment, the invention comprises a mechanical shutter disposed in a discharge opening between the arc chamber and the plasma guide tube of the implanter. The bore size of the shutter can be selectively varied in order to control the emission of electrons from the arc chamber into the ion beam in the plasma guide tube. In another embodiment, the invention comprises an electron-attracting probe which is disposed in the discharge opening.

Abstract: A method for improving an electrodeposited metal film uniformity and preventing metal deposition and peeling of deposited metal from an electrode during an electrodeposition and electropolishing process including providing a first anode electrode assembly and a semiconductor wafer plating surface disposed in an electrolyte bath including a plating metal for deposition onto the semiconductor wafer plating surface; providing at least one additional anode electrode assembly including the plating metal disposed peripheral to the first anode electrode assembly for selectively applying the cathodic electrical potential during an electropolishing process; and, periodically alternating between an electrodeposition process and electropolishing process with respect to the semiconductor wafer plating surface such that the plating metal is preferentially plated onto the at least one additional electrode assembly.

Abstract: Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

Abstract: A chemical mechanical polisher that is equipped with a chilled wafer holder and a chilled polishing pad and a method for operating the chemical mechanical polisher are described. A first heat exchanging fluid is flown into a membrane chamber inside the wafer holder in intimate contact with the backside of the wafer such that the wafer can be sufficiently cooled. A second heat exchanging fluid is circulated in a plurality of surface grooves, or fluid channels provided in the bottom surface of the polishing pad to sufficiently cool the polishing pad during a chemical mechanical polishing process. The slurry suspension contained in-between the wafer surface and the polishing pad can thus be sufficiently cooled.

Abstract: A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier gas such as argon or helium, but without an oxygen containing gas or a carbon and oxygen containing gas. The plasma etch method is selective for the etch stop layer with respect to the metal silicide layer, thus maintaining the physical and electrical integrity of the metal silicide layer.

Abstract: Utilizing contact printing as the second exposure within a double exposure attenuated phase shift mask (APSM) fabrication process is disclosed. The process defines the shift pattern within the attenuated layer of the APSM using a first exposure, such as electron beam (e-beam) writing. The attenuated layer may be MoSi, MoSiO, and so on. The process then defines the border pattern within the opaque layer of the APSM using a second exposure. The second exposure employs contact printing, utilizing a contact exposure mask. The contact printing process may align the contact exposure mask over the wafer on which the APSM is fabricated utilizing a camera and an image storage system storing an image of this wafer.

Abstract: The correction of improper leveling tilt induced by a leveling sensor of a semiconductor equipment improperly detecting a semiconductor wafer having an asymmetrical semiconductor pattern as out of horizontal is disclosed. The improper leveling tilt is determined, and a corrective leveling tilt is applied to compensate for the improper leveling tilt induced by the leveling sensor. The improper leveling tilt can be determined as the experimentally determined difference in focus between dense features of the asymmetrical pattern divided by the experimentally determined distance between the dense features. The improper leveling tilt can also be modeled as the difference in height between dense features and isolated features of the asymmetrical pattern, times a predetermined parameter, and divided by the field-of-view length of the leveling sensor.

Abstract: An anti-electrostatic discharge spray gun apparatus and method for preventing crystallization of particles formed as a result of electrostatic discharge from forming on a spray gun nozzle and an associated pair of oppositely charged electrodes disposed on the gun. The apparatus has a housing; a nozzle attached to the housing for dispensing gas; a device for dispensing a gas through the nozzle; a device for electrostatically discharging a gas dispensed through the nozzle; and a device for restricting the flow of a gas through the nozzle. The device for dispensing and restricting flow of a gas through the nozzle may be either a bypass piping having a flow control means or a stopper that operates to provide a constant but low volume flow of an inert gas such as nitrogen to the nozzle to prevent particle build up or crystallization from occurring.

Abstract: In general, the present invention provides a seismic emergency response system (SERS) to control fabrication equipment and material flow for prevention of damage to wafers and equipment within a wafer fabrication plant during an earthquake. The SERS having a facility manager control system having one or a plurality of seismic detection devices, and at least one voting logic device for outputting an alarm triggering signal to a computer integrated manufacturing system; and a computer integrated manufacturing system having an emergency response system and an equipment server (tool application program) for sending a pause equipment command to an associated piece of equipment and a hold lot command to a material execution system to prevent damage of wafers during an earthquake. Optionally provided is one or a plurality of false alarm prevention devices and one or a plurality of enabling switches provided to selectively enable or disable the SERS.

Abstract: A method and apparatus for monitoring an extraction electrode utilized in the implantation of charged particles (i.e., ions) on a semiconductor wafer. A signal may be generated from an encoder associated with the extraction electrode, wherein the signal comprises data indicative of charged particles attracted to and accelerated by the extraction electrode. The signal may then be analyzed either manually or automatically to determine if the extraction electrode is located at a position appropriate to attract and accelerate the charged particles to an acceleration tube for proper implantation thereof upon the semiconductor wafer. A main controller may be linked to the extraction electrode, wherein the main controller controls a location of the extraction electrode in proximity to the charged particles.

Abstract: An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.

Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma etching process including collecting data versus time during a plasma etching process the data including information representative of a concentration of at least one pair of reactant and product species present during the course of the plasma etching process; calculating a selected ratio of at least one reactant species and one product species at selected time intervals in the plasma etching process to create real-time concentration ratio data; retrieving model concentration ratio data for the at least one reactant species and one product species for comparison with the real-time concentration ratio data; comparing the model concentration ratio data with the real-time concentration ratio data to determine a difference; and, adjusting at least one plasma process operating parameter to minimize the difference.

Abstract: An interlock controller provides real time monitoring of the flow of gases or fluids into a semiconductor processing chamber and interrupts the flow when the peak flow exceeds a predetermined level. The controller receives signals from a mass flow control valve, respectively representing a commanded flow rate and an actual flow rate. The difference between these two signals is calculated and if the difference exceeds a certain value, a measurement cycle is initiated during which the peak flow rate is measured. If the measured peak low rate is greater than a predetermined value, then the controller closes a shut off vale to interrupt the flow into the chamber.

Abstract: A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

Abstract: An inking apparatus including an inking head which is manually adjustable in the X, Y and Z directions to facilitate quick and easy positioning of an inking probe in proximity to a defective die on a semiconductor wafer to ink and mark the die for exclusion from further processing. A horizontal positioning plate is horizontally adjustably mounted on a base plate, and an angular adjustment arm is angularly adjustably mounted on the horizontal positioning plate. The inking head is vertically adjustably mounted on the end of the angular adjustment arm and carries an ink reservoir from which ink is dispensed through an inking probe to the dies on the wafer.